Abstract: A cylindrical capacitor structure and a corresponding method of manufacture. To form the cylindrical capacitor, a conductive section, an etching stop layer, a first insulation layer, a bit line structure and a second insulation layer are sequentially formed over a substrate. A portion of the second insulation layer and the first insulation layer is removed until the etching stop layer is exposed. Ultimately, a plurality of gap-connected cylindrical openings and node contact openings between spacers are sequentially formed. Conductive spacers are formed on the sidewalls of the cylindrical openings and the node contact openings. In the meantime, material similar to the conductive spacers fills the small gaps, thereby forming an upper electrode for the capacitor. A dielectric layer is formed over the capacitor electrode. The exposed etching stop layer at the bottom of the contact opening is removed to expose the conductive section above the substrate.

Abstract: A cylindrical capacitor structure and a corresponding method of manufacture. To form the cylindrical capacitor, a conductive section, an etching stop layer, a first insulation layer, a bit line structure and a second insulation layer are sequentially formed over a substrate. A portion of the second insulation layer and the first insulation layer is removed until the etching stop layer is exposed. Ultimately, a plurality of gap-connected cylindrical openings and node contact openings between spacers are sequentially formed. Conductive spacers are formed on the sidewalls of the cylindrical openings and the node contact openings. In the meantime, material similar to the conductive spacers fills the small gaps, thereby forming an upper electrode for the capacitor. A dielectric layer is formed over the capacitor electrode. The exposed etching stop layer at the bottom of the contact opening is removed to expose the conductive section above the substrate.

Abstract: A method for minimizing damage of process charging phenomena during fabrication of integrated circuits is proposed by the invention. The presented method comprises following essential steps: First, provides a substrate and defines a plurality of cell regions and a plurality of scribe lines on the substrate, where any cell region is separated from other cell regions by these scribe lines. Second, forms a plurality of basic structures inside cell regions, where these basic structures are formed in and on the substrate. Third, forms an interpoly dielectric layer on the substrate, where the interpoly dielectric layer is located inside both cell regions and scribe lines. Fourth, forms a plurality of via holes inside scribe lines where bottom of any via hole is below surface of the substrate and top of any said via hole is on surface of the interpoly dielectric layer. Fifth, forms a conductive layer on the interpoly dielectric layer, where the conductive layer also fills these via holes.

Abstract: A method of defining a mask pattern for a photoresist layer in semiconductor fabrication. The method coats a photoresist layer containing an additive on a dielectric layer. The photoresist layer has an opening formed therein. The additive is 2,2′-azo-bis-isobutyronitride (AIBN) or phenyl-azo-triphenylmethane. The photoresist layer is exposed and developed. Then, a hard baking step is performed. A UV curing or a hot curing step is performed on the photoresist layer. As a result, the additive in the photoresist layer reacts to form nitrogen (N2) gas. Nitrogen gas makes the photoresist layer expand. The opening is decreased by the expansion of the photoresist layer. The dielectric layer is etched according to the expanded photoresist layer so that a via or a trench, which is smaller than a conventional one, is formed.

Abstract: A new method for forming integrated circuits is disclosed. The method includes the following procedures. A substrate over which a high integration region and a low integration region beside the high integration region are formed. Then dummy layer is formed on the low integration region. Next, a dielectric layer is formed on the high integration region and the dummy layer on the low integration region. Finally, the dielectric layer is planarized.

Abstract: A method of fabricating a bottom electrode is described. A substrate having a first conductive layer therein is provided. A first dielectric layer is formed over the substrate. A plurality bit lines is formed over the first dielectric layer. A conformal liner layer is formed over the first dielectric layer to cover the plurality bit lines. A second dielectric layer is formed over the conformal liner layer. An opening is formed in the second dielectric layer. The opening exposes a portion of the conformal liner layer between the bit lines and the conformal liner layer on portions of the bit lines. A conductive spacer is formed on a sidewall of the opening to expose a portion of the conformal liner layer between the bit lines. The exposed portion of the conformal liner layer between the bit lines is removed. The first dielectric layer exposed by the conductive spacer and the second dielectric layer are removed to form a node contact opening in the first dielectric layer.

Abstract: A method of fabricating a bottom electrode is described. A first dielectric layer having a first opening is formed over a substrate. The first opening exposes a portion of a conductive layer in the substrate. A first liner layer is formed on a sidewall of the first opening. A conductive plug is formed in the opening. A plurality of bit lines are formed next to the first opening. A second liner layer is formed over the substrate to cover the bit lines, the first liner layer, and the conductive plug. A node contact opening is formed in the second liner layer to expose a portion of the conductive plug. A second dielectric layer is formed over the substrate. A second opening is formed in the second dielectric layer to expose the node contact opening and a portion of the second liner layer. A conformal conductive layer is formed in the opening.

Abstract: A method of fabricating a protection device. A contact resistor, or a protection diode and a contact resistor are formed in a substrate. The protection diode and the contact resistor are electrically connected to a gate of a MOS so as to protect the MOS from being damaged by plasma. A multi-level interconnect is formed on the substrate, while a top metal layer of the multi-level interconnect is patterned, the electrical connection between the gate and the protection device is broken.

Abstract: A silicon oxide layer is first formed on a silicon substrate. Then, a polysilicon layer is formed on a predetermined area of the silicon oxide layer and a first dielectric layer is formed on top of the polysilicon layer. Next, a second dielectric layer is uniformly covered on the surface of the silicon oxide layer, the polysilicon layer and the first dielectric layer. An etching back process is performed to completely remove the second dielectric layer positioned on top of the first dielectric layer and to make the second dielectric layer positioned around the periphery of the polysilicon layer and the first dielectric layer become spacers. An etching process is performed to completely remove the first dielectric layer between the spacers. An ion implantation process is performed to form two doping areas in the silicon substrate adjacent to the spacers which are respectively used as a source and a drain of the MOS transistor.

Abstract: A method of fabricating a contact window. On semiconductor substrate having a conductive region, a dielectric layer is formed to cover the substrate and the conductive region. A gettering layer is formed on the dielectric layer. A hard mask layer is formed on the gettering layer. The hard mask layer is patterned to expose a part of the gettering layer which is right on top of the conductive region. The exposed gettering layer and the dielectric layer under the exposed gettering layer are removed to form the contact window.

Abstract: A method of enhancing chemical mechanical polishing uniformity is provided. In the fabrication of a shallow trench isolation structure, there are active area regions with different integration formed in a chip. The integration of the active area regions in the chip is computed according circuit designs by a program analysis. One of the active area regions with the highest integration is used as a basis, dummy mesas are formed in the other active area regions to adjust the integration of the chip.

Abstract: An ion implantation method useful for fabricating shallow trench isolation structureimplants phosphorus ions instead of arsenic ions into a substrate when the source/drain regions of an NMOS device are doped. Alternatively, low energy ions are used in the ion implantation for forming the source/drain regions of an NMOS device. Consequently lattice dislocations of the crystal structure within a substrate is reduced and unwanted device leakage current is eliminated.

Abstract: The present invention provides a method of forming a self-aligned contact hole on a semiconductor wafer. The semiconductor wafer comprises a substrate, two gates positioned on the substrate, at least a doped area between the gates on the substrate and spacers on each of two opposite walls of each gate wherein the spacers between the gates are joined and cover the doped area. The method comprises forming a dielectric layer on the surface of the semiconductor wafer, the dielectric layer covering the gates and the spacers. A first etching process is performed to remove the dielectric layer above the doped area down to a predetermined depth to form an opening, the bottom of the opening comprising the spacers and an upper portion of the gates. Poly-silicon spacers are then formed on the interior walls of the opening, the poly-silicon spacers covering an upper portion of the spacers and the upper portion of the gates.

Abstract: A method of protecting a well at a floating stage. In a first conductive type substrate, a second conductive type well is formed. A first conductive type heavily doped region and a second conductive type heavily doped region are respectively formed in the first conductive type substrate and the second conductive type well. These two heavily doped regions are electrically connected with each at an early stage of fabrication process to provide a protection from being damaged during subsequent plasma process or other processes. While forming a top metal layer of a multi-level interconnect, these two heavily doped regions are disconnected, that is, open to each other, to obtain a better electrical characteristic of the device or the integrated circuit formed on the substrate.

Abstract: A method of fabricating a contact window. On semiconductor substrate having a conductive region, a dielectric layer is formed to cover the substrate and the conductive region. A gettering layer is formed on the dielectric layer. A hard mask layer is formed on the gettering layer. The hard mask layer is patterned to expose a part of the gettering layer which is right on top of the conductive region. The exposed gettering layer and the dielectric layer under the exposed gettering layer are removed to form the contact window.

Abstract: A method for reducing plasma charging damages is disclosed. The method includes the following steps: define cell regions and scribe line regions on a substrate. Then, form a trench region on one of the scribe line regions wherein the bottom part of the trench region is in contact with the substrate. Thereupon fill the trench region with polysilicon substances. After the filling, deposit a pad polysilicon layer on the trench region. Following the pad layer formation, construct an integrated circuit as routine practice. During the circuit fabrication, several channel regions are formed in connection with the pad layer. Next, fabricate various conductive structures on the scribe line regions and link them also to the channel regions. Any excess charge in the scribe line region would be collected by the conductive structures and directed by the channel region to the trench region for grounding.

Abstract: This invention provides a method of forming a landing pad on the drain and source of a MOS transistor. The MOS transistor is formed on a silicon substrate of a semiconductor wafer and comprises a gate on the silicon substrate with a spacer around its periphery portion, a drain and a source on the surface of the silicon substrate and on opposite sides of the gate. The method comprises forming a conductive layer of uniform thickness above the drain or source of the MOS transistor. The conductive layer is used as the landing pads for the drain or source. The height of the conductive layer is lower than that of the spacer surrounding the gate so that the spacer electrically isolates the gate and the conductive layer.

Abstract: A method for forming a semiconductor device with avoiding chemical mechanical polishing caused residue on uncompleted fields of wafer edge is disclosed. The method comprising removing all conductive layers and silicon nitride layers on the uncompleted fields, thereby the height of the uncompleted fields will not higher than the height of the semiconductor device.

Abstract: A method for forming a shallow trench isolation used to isolate a device is provided. A pad oxide and a mask layer are formed on a substrate and patterned. A trench is formed within the substrate under the patterned region and the trench is filled with insulator to form an insulation plug, which is a shallow trench isolation. A dielectric layer is formed on the whole substrate surface to cover the device region and the insulation plug.

Abstract: A method of dual damascene includes forming a first conducting layer on a substrate, which already contains formed devices, and then forming a first dielectric layer and a hard material layer on the first conducting layer. The hard material layer contains a first opening, which is located right over the first conducting layer. A second dielectric layer is formed on the hard material layer, wherein the second dielectric layer is enforced by a ion implantation process or a plasma process. A hard mask layer containing a second opening is then formed on the second dielectric layer, wherein the second opening gradually widens upward, and wherein the second opening is located over the first opening. The hard mask layer is then used to pattern the second dielectric layer to expose the hard material layer. A part of the first dielectric layer is removed to expose the first conducting layer and form a third opening after a protection layer is formed on the side wall of the second dielectric layer.