Abstract: An optical coupler structure may include a substrate, a waveguide section and an anchored cantilever section. The substrate may include a main body and a sub-pillar structure formed on the main body. The waveguide section may be disposed on the substrate, and may include a core waveguide of a first material surrounded by a cladding layer of a second material. The anchored cantilever section may be disposed on the sub-pillar structure on the substrate, which may be configured to support the cantilever section and separate the cantilever section from the main body of the substrate. The anchored cantilever section may include a multi-stage inverse taper core waveguide and a cladding layer, of the second material, which surrounds the multi-stage inverse taper core waveguide.

Abstract: A compact and highly efficient coupling structure for coupling between DFB-LD and Si PIC edge coupler with suppressed return loss may include a DFB-LD, a Si PIC comprising at least one input edge coupler and at least one output edge coupler, a silica cover lid disposed on the Si PIC and aligned edge to edge with the Si PIC, a single-mode fiber aligned to the at least one output edge coupler of the Si PIC, a lens disposed between the DFB-LD and the at least one input edge coupler of the Si PIC, and an isolator bonded to a facet of the at least one input edge coupler with a first volume of an index matching fluid. The lens may be configured to minimize a mismatch between an output spot size of the DFB-LD and a spot size of the at least one input edge coupler of the Si PIC.

Abstract: A ring optical modulator includes a SOI substrate, including at least first and second top silicon layers, and a silicon-based ring resonator formed on the SOI substrate. The silicon-based ring resonator includes first and second top silicon layers, a thin dielectric gate layer disposed between the top silicon layers, first and second electric contacts, and first rib-type waveguide and ring-shape rib-type waveguide formed on the second top silicon layer. The thin dielectric layer includes a first side in contact with the first top silicon layer and a second side in contact with the second top silicon layer. With electric signals applied on the electric contacts, free carriers accumulate, deplete or invert within the top silicon layers on the first and second sides of the thin dielectric gate layer beneath the ring-shape rib-type waveguide, simultaneously, and a refractive index of the ring-shape rib-type waveguide confining optical fields is modulated.

Abstract: An optical package for providing efficient coupling between a photonic device and a silicon photonic integrated-circuit chip (Si PIC) edge couplers with low return loss, as well as variations thereof, is described. The optical package may include a photonic device, a Si PIC, a single mode fiber or fiber array assembly, a lens and a spacer. The Si PIC may an input edge coupler and an output edge coupler. The single mode fiber or fiber array assembly may be aligned to the output edge coupler. The lens may be disposed between the photonic device and the input edge coupler, and may be configured to minimize a mismatch between an output spot size of the photonic device and a spot size of the input edge coupler of the Si PIC. The spacer may be bonded to a facet of the input edge coupler with an index matching fluid.

Abstract: An optical package for providing efficient coupling between a distributed feedback laser diode (DFB-LD) and a silicon photonic integrated-circuit chip (Si PIC) edge couplers with low return loss, as well as variations thereof, is described. The optical package may include a DFB-LD, a Si PIC, a single mode fiber or fiber array assembly, a lens and a spacer. The Si PIC may include an input edge coupler and an output edge coupler. The single mode fiber or fiber array assembly may be aligned to the output edge coupler. The lens may be disposed between the DFB-LD and the input edge coupler, and may be configured to minimize a mismatch between an output spot size of the DFB-LD and a spot size of the input edge coupler of the Si PIC. The spacer may be bonded to a facet of the input edge coupler with an index matching fluid.

Abstract: Avalanche photodiodes (APDs) having at least one top stressor layer disposed on a germanium (Ge) absorption layer are described herein. The top stressor layer can increase the tensile strain of the Ge absorption layer, thus extending the absorption of APDs to longer wavelengths beyond 1550 nm. In one embodiment, the top stressor layer has a four-layer structure, including an amorphous silicon (Si) layer disposed on the Ge absorption layer; a first silicon dioxide (SiO2) layer disposed on the amorphous Si layer, a silicon nitride (SiN) layer disposed on the first SiO2 layer, and a second SiO2 layer disposed on the SiN layer. The Ge absorption layer can be further doped by p-type dopants. The doping concentration of p-type dopants is controlled such that a graded doping profile is formed within the Ge absorption layer to decrease the dark currents in APDs.

Abstract: Various embodiments of a compensated photonic device structure and fabrication method thereof are described herein. A photonic device may include a silicon-on-insulator (SOI) substrate with a buried oxide (BOX) layer therein, a Si waveguide and an n-type contact layer formed on the BOX layer, a Si multiplication layer disposed on the n-type contact layer, a p-type Si charge layer disposed on the Si multiplication layer, a germanium (Ge) absorption layer disposed on the p-type Si charge layer, a p-type contact layer disposed on the Ge absorption layer, and a metal layer disposed on the p-type contact layer. A compensated region may be formed between the p-type Si charge layer and the Ge absorption layer with a portion of the compensated region in the p-type Si charge layer and another portion of the compensated region in the Ge absorption layer.

Abstract: A compact and highly efficient coupling structure for coupling between DFB-LD and Si PIC edge coupler with suppressed return loss may include a DFB-LD, a Si PIC comprising at least one input edge coupler and at least one output edge coupler, a silica cover lid disposed on the Si PIC and aligned edge to edge with the Si PIC, a single-mode fiber aligned to the at least one output edge coupler of the Si PIC, a lens disposed between the DFB-LD and the at least one input edge coupler of the Si PIC, and an isolator bonded to a facet of the at least one input edge coupler with a first volume of an index matching fluid. The lens may be configured to minimize a mismatch between an output spot size of the DFB-LD and a spot size of the at least one input edge coupler of the Si PIC.

Abstract: A ring optical modulator includes a SOI substrate, including at least first and second top silicon layers, and a silicon-based ring resonator formed on the SOI substrate. The silicon-based ring resonator includes first and second top silicon layers, a thin dielectric gate layer disposed between the top silicon layers, first and second electric contacts, and first rib-type waveguide and ring-shape rib-type waveguide formed on the second top silicon layer. The thin dielectric layer includes a first side in contact with the first top silicon layer and a second side in contact with the second top silicon layer. With electric signals applied on the electric contacts, free carriers accumulate, deplete or invert within the top silicon layers on the first and second sides of the thin dielectric gate layer beneath the ring-shape rib-type waveguide, simultaneously, and a refractive index of the ring-shape rib-type waveguide confining optical fields is modulated.

Abstract: An optical package for providing efficient coupling between a distributed feedback laser diode (DFB-LD) and a silicon photonic integrated-circuit chip (Si PIC) edge couplers with low return loss, as well as variations thereof, is described. The optical package may include a DFB-LD, a Si PIC, a single mode fiber or fiber array assembly, a lens and a spacer. The Si PIC may include an input edge coupler and an output edge coupler. The single mode fiber or fiber array assembly may be aligned to the output edge coupler. The lens may be disposed between the DFB-LD and the input edge coupler, and may be configured to minimize a mismatch between an output spot size of the DFB-LD and a spot size of the input edge coupler of the Si PIC. The spacer may be bonded to a facet of the input edge coupler with an index matching fluid.

Abstract: Various structures of an electro-optic device and fabrication methods thereof are described. A fabrication method is provided to fabricate an electro-optic device which may include a silicon-based rib-waveguide modulator which includes a first top silicon layer, having a first doped region that is at least partially doped with dopants of a first conducting type, a second top silicon layer, having a second doped region that is at least partially doped with dopants of a second conducting type, and a thin dielectric gate layer disposed between the first top silicon layer and the second top silicon layer. The second doped region may be at least in part directly over the first doped region. The modulator may also include a rib waveguide formed on the second top silicon layer, a first electric contact formed on the first top silicon layer, and a second electric contact formed on the second top silicon layer.

Abstract: An optical coupler structure may include a substrate, a waveguide section and an anchored cantilever section. The substrate may include a main body and a sub-pillar structure formed on the main body. The waveguide section may be disposed on the substrate, and may include a core waveguide of a first material surrounded by a cladding layer of a second material. The anchored cantilever section may be disposed on the sub-pillar structure on the substrate, which may be configured to support the cantilever section and separate the cantilever section from the main body of the substrate. The anchored cantilever section may include a multi-stage inverse taper core waveguide and a cladding layer, of the second material, which surrounds the multi-stage inverse taper core waveguide.

Abstract: Various structures of an electro-optic device and fabrication methods thereof are described. A fabrication method is provided to fabricate an electro-optic device which may include a silicon-based rib-waveguide modulator which includes a first top silicon layer, having a first doped region that is at least partially doped with dopants of a first conducting type, a second top silicon layer, having a second doped region that is at least partially doped with dopants of a second conducting type, and a thin dielectric gate layer disposed between the first top silicon layer and the second top silicon layer. The second doped region may be at least in part directly over the first doped region. The modulator may also include a rib waveguide formed on the second top silicon layer, a first electric contact formed on the first top silicon layer, and a second electric contact formed on the second top silicon layer.

Abstract: A method of fabricating an integrated structure for MEMS device and semiconductor device comprises steps of: providing a substrate having a transistor thereon in a semiconductor device region and a first MEMS component thereon in a MEMS region; performing a interconnect process on the substrate in the semiconductor device region to form a plurality of first dielectric layers, at least a conductive plug and at least a conductive layer in the first dielectric layers; forming a plurality of second dielectric layers and an etch stopping device in the second dielectric layers on the substrate in a etch stopping device region; forming a plurality of third dielectric layers and at least a second MEMS component in the third dielectric layers on the substrate in the MEMS region; and performing an etching process to remove the third dielectric layers in the MEMS region.

Abstract: The present invention relates to an integrated structure for a MEMS device and a semiconductor device and a method of fabricating the same, in which an etch stopping element is included on a substrate between the MEMS device and the semiconductor device for protecting the semiconductor device from lateral damage when an oxide releasing process is performed to fabricate the MEMS device. The etch stopping element has various profiles and is selectively formed by an individual fabricating process or is simultaneously formed with the semiconductor device in the same fabricating process. It is a singular structure or a combined stacked multilayered structure, for example, a plurality of rows of pillared etch-resistant material plugs, one or a plurality of wall-shaped etch-resistant material plugs, or a multilayered structure of a stack of which and an etch-resistant material layer.

Abstract: A method of fabricating a MEMS microphone includes: first providing a substrate having a first surface and a second surface. The substrate is divided into a logic region and a MEMS region. The first surface of the substrate is etched to form a plurality of first trenches in the MEMS region. An STI material is then formed in the plurality of first trenches. Subsequently, the second surface of the substrate is etched to form a second trench in the MEMS region, wherein the second trench connects with each of the first trenches. Finally, the STI material in the first trenches is removed.

Abstract: Avalanche photodiodes (APDs) having at least one top stressor layer disposed on a germanium (Ge) absorption layer are described herein. The top stressor layer can increase the tensile strain of the Ge absorption layer, thus extending the absorption of APDs to longer wavelengths beyond 1550 nm. In one embodiment, the top stressor layer has a four-layer structure, including an amorphous silicon (Si) layer disposed on the Ge absorption layer; a first silicon dioxide (SiO2) layer disposed on the amorphous Si layer, a silicon nitride (SiN) layer disposed on the first SiO2 layer, and a second SiO2 layer disposed on the SiN layer. The Ge absorption layer can be further doped by p-type dopants. The doping concentration of p-type dopants is controlled such that a graded doping profile is formed within the Ge absorption layer to decrease the dark currents in APDs.

Abstract: A micro electro mechanical system (MEMS) structure is disclosed. The MEMS structure includes a backplate electrode and a 3D diaphragm electrode. The 3D diaphragm electrode has a composite structure so that a dielectric is disposed between two metal layers. The 3D diaphragm electrode is adjacent to the backplate electrode to form a variable capacitor together.

Abstract: An integrated circuit (IC) having a microelectromechanical system (MEMS) device buried therein is provided. The integrated circuit includes a substrate, a metal-oxide semiconductor (MOS) device, a metal interconnect, and the MEMS device. The substrate has a logic circuit region and a MEMS region. The MOS device is located on the logic circuit region of the substrate. The metal interconnect, formed by a plurality of levels of wires and a plurality of vias, is located above the substrate to connect the MOS device. The MEMS device is located on the MEMS region, and includes a sandwich membrane located between any two neighboring levels of wires in the metal interconnect and connected to the metal interconnect.

Abstract: A fabricating method of integrated circuit is provided. During the fabricating process of an interconnecting structure of the integrated circuit, a micro electromechanical system (MENS) diaphragm is formed between two adjacent dielectric layers of the interconnecting structure. The method of forming the MENS diaphragm includes the following steps. Firstly, a plurality of first openings is formed within any dielectric layer to expose corresponding conductive materials of the interconnecting structure. Secondly, a bottom insulating layer is formed on the dielectric layer and filling into the first openings. Third, portions of the bottom insulating layer located in the first openings are removed to form at least a first trench for exposing the corresponding conductive materials. Then, a first electrode layer and a top insulating layer are sequentially formed on the bottom insulating layer, and the first electrode layer filled into the first trench and is electrically connected to the conductive materials.