Patents by Inventor Tzung-I Su

Tzung-I Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8558336
    Abstract: A semiconductor photodetector structure is provided. The structure includes a substrate, a photodetecting element and a semiconductor layer disposed on the photodetecting element. The substrate includes a first semiconductor material and includes a deep trench. The surface of the deep trench includes a first type dopant. The photodetecting element is disposed in the deep trench. The photodetecting element includes a second semiconductor material. The semiconductor layer includes a second type dopant.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: October 15, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Tzung-I Su, Bang-Chiang Lan, Chao-An Su, Hui-Min Wu, Ming-I Wang, Chien-Hsin Huang, Tzung-Han Tan, Min Chen, Meng-Jia Lin, Wen-Yu Su
  • Patent number: 8502382
    Abstract: A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: August 6, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Bang-Chiang Lan, Ming-I Wang, Hui-Min Wu, Min Chen, Chien-Hsin Huang, Tzung-I Su, Chao-An Su, Tzung-Han Tan, Li-Che Chen, Meng-Jia Lin
  • Patent number: 8384214
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a dielectric layer, a pad structure and a protection structure. The dielectric layer is disposed on the substrate. The pad structure is disposed in the dielectric layer. The pad structure includes a plurality of first metal layers and a plurality of plugs which are electrically connected to each other vertically. There is no contact plug disposed between the pad structure and the substrate. The protection structure is disposed in the dielectric layer and encompasses the pad structure.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: February 26, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Hui-Min Wu, Bang-Chiang Lan, Ming-I Wang, Tzung-I Su, Chien-Hsin Huang, Chao-An Su, Tzung-Han Tan, Min Chen, Meng-Jia Lin
  • Patent number: 8368153
    Abstract: A wafer level package of micro electromechanical system (MEMS) microphone includes a substrate, a number of dielectric layers stacked on the substrate, a MEMS diaphragm, a number of supporting rings and a protective layer. The MEMS diaphragm is disposed between two adjacent dielectric layers. A first chamber is between the MEMS diaphragm and the substrate. The supporting rings are disposed in some dielectric layers and stacked with each other. An inner diameter of the lower supporting ring is greater than that of the upper supporting ring. The protective layer is disposed on the upmost supporting ring and covers the MEMS diaphragm. A second chamber is between the MEMS diaphragm and the protective layer. The protective layer defines a number of first through holes for exposing the MEMS diaphragm. The wafer level package of MEMS microphone has an advantage of low cost.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: February 5, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Hsin Huang, Li-Che Chen, Ming-I Wang, Bang-Chiang Lan, Hui-Min Wu, Tzung-I Su
  • Patent number: 8310065
    Abstract: A fabrication method of a wafer structure includes: providing a substrate having a plurality of die regions and an edge region surrounding the die regions defined thereon; then, forming a dielectric layer, a plurality of MEMS devices, a plurality of metal-interconnect structures and a plurality bonding pads on the substrate in the die regions; next, removing the dielectric layer disposed on the substrate of the edge region to expose the substrate; and thereafter, forming a passivation layer to cover the substrate and the dielectric layer.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: November 13, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Hui-Min Wu, Bang-Chiang Lan, Chien-Hsin Huang, Kuan-Yu Wang, Chao-An Su, Tzung-I Su
  • Patent number: 8299555
    Abstract: A method of fabricating a semiconductor optoelectronic structure is provided. First, a substrate is provided, and a waveguide is formed therein, and then a plurality of dielectric layers is formed on the waveguide. Next, a contact pad and a passivation layer are provided on the dielectric layers and a patterned mask layer is formed thereon. Last, an etching process is provided by using the patterned mask layer to expose the contact pad and remove a portion of the passivation layer and the dielectric layers to form a transformer.
    Type: Grant
    Filed: November 15, 2009
    Date of Patent: October 30, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Tzung-I Su, Chao-An Su, Ming-I Wang, Bang-Chiang Lan, Tzung-Han Tan, Hui-Min Wu, Chien-Hsin Huang, Min Chen, Meng-Jia Lin
  • Publication number: 20120205808
    Abstract: A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.
    Type: Application
    Filed: April 30, 2012
    Publication date: August 16, 2012
    Inventors: Bang-Chiang Lan, Ming-I Wang, Hui-Min Wu, Min Chen, Chien-Hsin Huang, Tzung-I Su, Chao-An Su, Tzung-Han Tan, Li-Che Chen, Meng-Jia Lin
  • Publication number: 20120175778
    Abstract: A fabrication method of a wafer structure includes: providing a substrate having a plurality of die regions and an edge region surrounding the die regions defined thereon; then, forming a dielectric layer, a plurality of MEMS devices, a plurality of metal-interconnect structures and a plurality bonding pads on the substrate in the die regions; next, removing the dielectric layer disposed on the substrate of the edge region to expose the substrate; and thereafter, forming a passivation layer to cover the substrate and the dielectric layer.
    Type: Application
    Filed: January 6, 2011
    Publication date: July 12, 2012
    Inventors: Hui-Min Wu, Bang-Chiang Lan, Chien-Hsin Huang, Kuan-Yu Wang, Chao-An Su, Tzung-I Su
  • Patent number: 8208768
    Abstract: A focusing member and an optoelectronic device having the same are provided. The focusing member includes multiple levels of conductive plugs and multiple levels of conductive layers that together form an inversed half-boat shape. The optoelectronic device includes a bottom layer, an optical waveguide above the bottom layer, a dielectric layer covering the optical waveguide, and the above focusing member disposed at an edge of the optoelectronic device and located in the dielectric layer above the optical waveguide. A wider end of the inversed half-boat shape of the focusing member faces the outside of the optoelectronic device. The refractive indexes of the bottom layer and the dielectric layer are smaller than that of the optical waveguide.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: June 26, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Tzung-I Su, Ming-I Wang, Bang-Chiang Lan, Te-Kan Liao, Chao-An Su, Hui-Min Wu, Chien-Hsin Huang, Tzung-Han Tan, Min Chen, Meng-Jia Lin
  • Patent number: 8193640
    Abstract: A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: June 5, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Bang-Chiang Lan, Ming-I Wang, Hui-Min Wu, Min Chen, Chien-Hsin Huang, Tzung-I Su, Chao-An Su, Tzung-Han Tan, Li-Che Chen, Meng-Jia Lin
  • Patent number: 8139907
    Abstract: An optoelectronic device including a substrate, a half-boat-shaped material layer, a deep trench isolation structure, and an optical waveguide is provided. The substrate has a first area. The half-boat-shaped material layer is disposed in the substrate within the first area. The refractive index of the half-boat-shaped material layer is lower than that of the substrate. A top surface of the half-boat-shaped material layer is coplanar with the surface of the substrate. The deep trench isolation structure is disposed in the substrate within the first area and located at one side of a bow portion of the half-boat-shaped material layer. The optical waveguide is disposed on the substrate within the first area. The optical waveguide overlaps a portion of the deep trench isolation structure and at least a portion of the half-boat-shaped material layer.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: March 20, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Tzung-I Su, Ming-I Wang, Bang-Chiang Lan, Te-Kan Liao, Chao-An Su, Chien-Hsin Huang, Hui-Min Wu, Tzung-Han Tan, Min Chen, Meng-Jia Lin
  • Patent number: 8096048
    Abstract: A method for fabricating a MEMS is described as follows. A substrate is provided, including a circuit region and a MEMS region separated from each other. A first metal interconnection structure is formed on the substrate in the circuit region, and simultaneously a first dielectric structure is formed on the substrate in the MEMS region. A second metal interconnection structure is formed on the first metal interconnection structure, and simultaneously a second dielectric structure, at least two metal layers and at least one protection ring are formed on the first dielectric structure. The metal layers and the protection ring are formed in the second dielectric structure and the protection ring connects two adjacent metal layers to define an enclosed space between two adjacent metal layers. The first dielectric structure and the second dielectric structure outside the enclosed space are removed to form a MEMS device in the MEMS region.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: January 17, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Bang-Chiang Lan, Ming-I Wang, Li-Hsun Ho, Hui-Min Wu, Min Chen, Chien-Hsin Huang, Tzung-I Su
  • Publication number: 20110248364
    Abstract: A wafer level package of micro electromechanical system (MEMS) microphone includes a substrate, a number of dielectric layers stacked on the substrate, a MEMS diaphragm, a number of supporting rings and a protective layer. The MEMS diaphragm is disposed between two adjacent dielectric layers. A first chamber is between the MEMS diaphragm and the substrate. The supporting rings are disposed in some dielectric layers and stacked with each other. An inner diameter of the lower supporting ring is greater than that of the upper supporting ring. The protective layer is disposed on the upmost supporting ring and covers the MEMS diaphragm. A second chamber is between the MEMS diaphragm and the protective layer. The protective layer defines a number of first through holes for exposing the MEMS diaphragm. The wafer level package of MEMS microphone has an advantage of low cost.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 13, 2011
    Inventors: Chien-Hsin Huang, Li-Che Chen, Ming-I Wang, Bang-Chiang Lan, Hui-Min Wu, Tzung-I Su
  • Publication number: 20110241137
    Abstract: A fabricating method of integrated circuit is provided. During the fabricating process of an interconnecting structure of the integrated circuit, a micro electromechanical system (MENS) diaphragm is formed between two adjacent dielectric layers of the interconnecting structure. The method of forming the MENS diaphragm includes the following steps. Firstly, a plurality of first openings is formed within any dielectric layer to expose corresponding conductive materials of the interconnecting structure. Secondly, a bottom insulating layer is formed on the dielectric layer and filling into the first openings. Third, portions of the bottom insulating layer located in the first openings are removed to form at least a first trench for exposing the corresponding conductive materials. Then, a first electrode layer and a top insulating layer are sequentially formed on the bottom insulating layer, and the first electrode layer filled into the first trench and is electrically connected to the conductive materials.
    Type: Application
    Filed: April 6, 2010
    Publication date: October 6, 2011
    Inventors: Chien-Hsin HUANG, Li-Che Chen, Ming-I Wang, Bang-Chiang Lan, Tzung-Han Tan, Hui-Min Wu, Tzung-I Su
  • Publication number: 20110189804
    Abstract: A method of fabricating a MEMS microphone includes: first providing a substrate having a first surface and a second surface. The substrate is divided into a logic region and a MEMS region. The first surface of the substrate is etched to form a plurality of first trenches in the MEMS region. An STI material is then formed in the plurality of first trenches. Subsequently, the second surface of the substrate is etched to form a second trench in the MEMS region, wherein the second trench connects with each of the first trenches. Finally, the STI material in the first trenches is removed.
    Type: Application
    Filed: February 3, 2010
    Publication date: August 4, 2011
    Inventors: Chien-Hsin Huang, Bang-Chiang Lan, Hui-Min Wu, Tzung-I Su, Chao-An Su, Tzung-Han Tan
  • Publication number: 20110158581
    Abstract: An optoelectronic device including a substrate, a half-boat-shaped material layer, a deep trench isolation structure, and an optical waveguide is provided. The substrate has a first area. The half-boat-shaped material layer is disposed in the substrate within the first area. The refractive index of the half-boat-shaped material layer is lower than that of the substrate. A top surface of the half-boat-shaped material layer is coplanar with the surface of the substrate. The deep trench isolation structure is disposed in the substrate within the first area and located at one side of a bow portion of the half-boat-shaped material layer. The optical waveguide is disposed on the substrate within the first area. The optical waveguide overlaps a portion of the deep trench isolation structure and at least a portion of the half-boat-shaped material layer.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tzung-I Su, Ming-I Wang, Bang-Chiang Lan, Te-Kan Liao, Chao-An Su, Chien-Hsin Huang, Hui-Min Wu, Tzung-Han Tan, Min Chen, Meng-Jia Lin
  • Publication number: 20110158582
    Abstract: A method of forming the structure of the semiconductor device having a waveguide. Firstly, a SOI substrate including a bulk silicon, an insulating layer, and a silicon layer is provided and a device region and a waveguide region are defined on the SOI substrate. Afterwards, a protection layer and a patterned shielding layer are formed to cover the waveguide region and expose the device region. Subsequently, a recess is formed by etching the protection layer, the silicon layer and the insulating layer and thereby the bulk silicon is exposed. After that, an epitaxial silicon layer is formed in the recess and a semiconductor device is subsequently formed on the epitaxial silicon layer. Also, the present invention conquers the poor electrical performance of the semiconductor device integrated into the SOI substrate.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Inventors: Tzung-I Su, Ming-I Wang, Bang-Chiang Lan, Te-Kan Liao, Chao-An Su, Chien-Hsin Huang, Hui-Min Wu, Tzung-Han Tan, Min Chen, Meng-Jia Lin
  • Publication number: 20110115039
    Abstract: A micro electro mechanical system (MEMS) structure is disclosed. The MEMS structure includes a backplate electrode and a 3D diaphragm electrode. The 3D diaphragm electrode has a composite structure so that a dielectric is disposed between two metal layers. The 3D diaphragm electrode is adjacent to the backplate electrode to form a variable capacitor together.
    Type: Application
    Filed: November 19, 2009
    Publication date: May 19, 2011
    Inventors: Chien-Hsin Huang, Bang-Chiang Lan, Ming-I Wang, Hui-Min Wu, Tzung-I Su, Chao-An Su, Tzung-Han Tan, Min Chen, Meng-Jia Lin
  • Publication number: 20110115040
    Abstract: A method of fabricating a semiconductor optoelectronic structure is provided. First, a substrate is provided, and a waveguide is formed therein, and then a plurality of dielectric layers is formed on the waveguide. Next, a contact pad and a passivation layer are provided on the dielectric layers and a patterned mask layer is formed thereon. Last, an etching process is provided by using the patterned mask layer to expose the contact pad and remove a portion of the passivation layer and the dielectric layers to form a transformer.
    Type: Application
    Filed: November 15, 2009
    Publication date: May 19, 2011
    Inventors: Tzung-I Su, Chao-An Su, Ming-I Wang, Bang-Chiang Lan, Tzung-Han Tan, Hui-Min Wu, Chien-Hsin Huang, Min Chen, Meng-Jia Lin
  • Publication number: 20110097033
    Abstract: A focusing member and an optoelectronic device having the same are provided. The focusing member includes multiple levels of conductive plugs and multiple levels of conductive layers that together form an inversed half-boat shape. The optoelectronic device includes a bottom layer, an optical waveguide above the bottom layer, a dielectric layer covering the optical waveguide, and the above focusing member disposed at an edge of the optoelectronic device and located in the dielectric layer above the optical waveguide. A wider end of the inversed half-boat shape of the focusing member faces the outside of the optoelectronic device. The refractive indexes of the bottom layer and the dielectric layer are smaller than that of the optical waveguide.
    Type: Application
    Filed: October 26, 2009
    Publication date: April 28, 2011
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tzung-I Su, Ming-I Wang, Bang-Chiang Lan, Te-Kan Liao, Chao-An Su, Hui-Min Wu, Chien-Hsin Huang, Tzung-Han Tan, Min Chen, Meng-Jia Lin