Abstract: An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a semiconductor substrate, a first well region, first, second and third doped regions, and a gate structure. The first well region having a first conductivity type is located in the semiconductor substrate. The first and second doped region having a second conductivity type are located on the first well region. The third doped region having the first conductivity type is located on the first well region. The second and third doped regions are located on opposite sides of the first doped region. The gate structure is disposed on a portion of the semiconductor substrate between the first and second doped regions. A conductivity type of the gate structure is different from a conductivity type of the first and second doped regions. The gate structure is electrically connected to the first and third doped regions.

Abstract: An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a semiconductor substrate, first and second well regions, and first and second heavily doped regions. The first and second well regions have a first conductivity type and are located in the semiconductor substrate. The first heavily doped region on the first well region has a second conductivity type. A first bottom of the first well region and a second bottom of the second well region are connected to each other and have different profiles. The first and second well regions have different doping concentrations. The second heavily doped region on the second well region has the first conductivity type. The first and second heavily doped regions are arranged side-by-side and are spaced apart from each other. The first heavily doped region is electrically connected to an input/output terminal.

Abstract: An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a P-type semiconductor substrate, P-type and N-type well regions, a deep N-type well region, first N-type and P-type doped regions, second N-type and P-type doped regions. The P-type and N-type well regions are located in the P-type semiconductor substrate. The deep N-type well region is located in the P-type semiconductor substrate and below the P-type well region. The first N-type and P-type doped regions are located on the P-type well region. The second N-type and P-type doped regions are located on the N-type well region. The first P-type doped region is electrically connected to the second N-type doped region.

Abstract: A method for fabricating a protection device includes forming a doped well with a first-type impurity in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.

Abstract: A method for fabricating a protection device includes forming a doped well with a first-type impurity in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.

Abstract: A protection device as provided includes a doped well with a first-type impurity, formed in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.

Abstract: A protection device as provided includes a doped well with a first-type impurity, formed in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.

Abstract: A method for fabricating microstrip line structure is disclosed. First, a substrate is provided, ground patterns are formed on the substrate, an interlayer dielectric (ILD) layer is formed on the ground patterns, contact plugs are formed in the ILD layer, a ground plate is formed on the ILD layer, and a signal line is formed on the ground plate. Preferably, the ground plate includes openings that are completely shielded by the ground patterns.

Abstract: A method for fabricating microstrip line structure is disclosed. First, a substrate is provided, ground patterns are formed on the substrate, an interlayer dielectric (ILD) layer is formed on the ground patterns, contact plugs are formed in the ILD layer, a ground plate is formed on the ILD layer, and a signal line is formed on the ground plate. Preferably, the ground plate includes openings that are completely shielded by the ground patterns.

Abstract: A waveguide structure includes a signal line and two static lines. The signal line is disposed between the static lines in a first direction. The static lines and the signal line are disposed parallel to one another. Each static line includes a first conductive pattern, a second conductive pattern, and a third conductive pattern. The first conductive pattern and the signal line are disposed on an identical plane of a dielectric layer. A thickness of the first conductive pattern is substantially equal to a thickness of the signal line. The second conductive pattern is disposed on the first conductive pattern. A width of the first conductive pattern is larger than a width of the second conductive pattern in the first direction. The third conductive pattern is disposed on the second conductive pattern. A width of the third conductive pattern is larger than the width of the second conductive pattern.

Abstract: A waveguide structure includes a signal line and two static lines. The signal line is disposed between the static lines in a first direction. The static lines and the signal line are disposed parallel to one another. Each static line includes a first conductive pattern, a second conductive pattern, and a third conductive pattern. The first conductive pattern and the signal line are disposed on an identical plane of a dielectric layer. A thickness of the first conductive pattern is substantially equal to a thickness of the signal line. The second conductive pattern is disposed on the first conductive pattern. A width of the first conductive pattern is larger than a width of the second conductive pattern in the first direction. The third conductive pattern is disposed on the second conductive pattern. A width of the third conductive pattern is larger than the width of the second conductive pattern.

Abstract: The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure.

Abstract: The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure.

Abstract: A cognitive radio communication network is provided. The cognitive radio communication network includes a cloud and a wireless communication network. A communication system accessing to a backbone network is provided. The communication system includes a cloud and a wireless communication network connected to the cloud, and having a plurality of cognitive radio access points and a plurality of users, wherein the cloud performs the functions of network management, power control, and radio resource management.

Abstract: The present invention provides a semiconductor structure, including a substrate, a first TSV, an inductor and a capacitor. The first TSV is disposed in the substrate and has a first signal. The inductor is disposed in the substrate. The capacitor is electrically connected to the inductor to form an LC circuit to bypass the noise from the first signal. The present invention further provides a method of reducing the signal noise in a semiconductor structure.

Abstract: A cognitive radio communication network is provided. The cognitive radio communication network includes a cloud and a wireless communication network. A communication system accessing to a backbone network is provided. The communication system includes a cloud and a wireless communication network connected to the cloud, and having a plurality of cognitive radio access points and a plurality of users, wherein the cloud performs the functions of network management, power control, and radio resource management.

Abstract: The present invention provides a semiconductor structure, including a substrate, a first TSV, an inductor and a capacitor. The first TSV is disposed in the substrate and has a first signal. The inductor is disposed in the substrate. The capacitor is electrically connected to the inductor to form an LC circuit to bypass the noise from the first signal. The present invention further provides a method of reducing the signal noise in a semiconductor structure.

Abstract: A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.

Abstract: A die seal ring disposed outside of a die region of a semiconductor substrate is disclosed. The die seal ring includes a first isolation structure, a second isolation structure, and at least one third isolation structure disposed between the first isolation structure and the second isolation structure; a plurality of first regions between the first isolation structure, the second isolation structure and the third isolation structure; a second region under the first region and the third isolation structure; and a third region under the first isolation structure.

Abstract: A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.