Abstract: A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielectric layer to cover a floating gate patterned on a semiconductor substrate. Oxide spacer are formed on the conductive layer adjacent to the sidewalls of the floating gate. Performing an anisotropic etch process on the conductive layer and using the oxide spacers as a hard mask, a conductive spacers are self-aligned fabricated at both sides of the floating gate, serving as sidewall control gates.

Abstract: A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielectric layer to cover a floating gate patterned on a semiconductor substrate. Oxide spacer are formed on the conductive layer adjacent to the sidewalls of the floating gate. Performing an anisotropic etch process on the conductive layer and using the oxide spacers as a hard mask, a conductive spacers are self-aligned fabricated at both sides of the floating gate, serving as sidewall control gates.

Abstract: A non-volatile memory and a method of fabricating the same are described. First, a substrate is provided. Then, a plurality of stack structures is formed on the substrate. Each stack structure comprises, from bottom to top, a bottom dielectric layer, a charge trapping layer, a top dielectric layer, a control gate and a cap layer. Next, a plurality of spacers is formed on the sidewalls of the stack structures. Thereafter, a gate dielectric layer is formed over the substrate. A word line is formed between two neighboring stack structures. After that, the cap layers in the stack structures are removed. A source and a drain are formed in the substrate beside the stack structures adjacent to the sides of each word line.

Abstract: A non-volatile memory cell is provided. The non-volatile memory includes a substrate, a gate stacked layer, an isolation layer and a conductive layer. The gate stacked layer includes a tunneling layer, a charge trapping layer, a barrier layer and a control gate layer sequentially stacked over the substrate, and the stacked gate layer has an opening therein through these layers. The isolation layer is located on the surface of the opening. The conductive layer is disposed in the opening to cover the isolation layer.

Abstract: A memory device including a plurality of word lines, a plurality of bit lines, at least four control lines and a plurality of memory cells is provided. The bit lines are disposed in a perpendicular direction of the word lines. Each memory cell is disposed at an intersection of one of the word lines and one of the bit lines, and every four sequential memory cells having a common word line are connected to the four control lines respectively. In addition, in each of the memory cells, the control line thereof is disposed between the bit line thereof and the word line thereof, and is parallel to the bit line thereof, wherein each of the memory cell is provided as a bit.

Abstract: The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region and a first P+ doped source region. The second PMOS transistor includes a gate and a second P+ doped source region. The first P+ doped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a N+ doped region. The floating gate overlaps with the N-well and extends to the N+ doped region. The overlapped region of the P-well and the N+ doped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.

Abstract: A method for programming a single-bit storage nonvolatile memory cell includes the steps of: providing a single-bit storage nonvolatile memory cell having a channel region between a left bit line and a right bit line, a composite dielectric layer for storing digital data, and a word line overlying the composite dielectric layer, performing a left side electron injection on the single-bit storage nonvolatile memory cell by applying a relatively high word line voltage to the word line, applying a relatively high left bit line voltage to the left bit line, and applying a relatively low right bit line voltage to the right bit line; and performing a right side electron injection by applying the relatively high word line voltage to the word line, applying a relatively low left bit line voltage to the left bit line, and applying a relatively high right bit line voltage to the right bit line.

Abstract: A memory device including a plurality of word lines, a plurality of bit lines, at least four control lines and a plurality of memory cells is provided. The bit lines are disposed in a perpendicular direction of the word lines. Each memory cell is disposed at an intersection of one of the word lines and one of the bit lines, and every four sequential memory cells having a common word line are connected to the four control lines respectively. In addition, in each of the memory cells, the control line thereof is disposed between the bit line thereof and the word line thereof, and is parallel to the bit line thereof, wherein each of the memory cell is provided as a bit.

Abstract: A method for programming a single-bit storage nonvolatile memory cell includes the steps of: providing a single-bit storage nonvolatile memory cell having a channel region between a left bit line and a right bit line, a composite dielectric layer for storing digital data, and a word line overlying the composite dielectric layer; performing a left side electron injection on the single-bit storage nonvolatile memory cell by applying a relatively high word line voltage (VWL, HIGH) to the word line, applying a relatively high left bit line voltage (VLBL, HIGH) to the left bit line, and applying a relatively low right bit line voltage (VRBL, LOW) to the right bit line; and performing a right side electron injection on the single-bit storage nonvolatile memory cell by applying the relatively high word line voltage (VWL, HIGH) to the word line, applying a relatively low left bit line voltage (VLBL, LOW) to the left bit line, and applying a relatively high right bit line voltage (VRBL, HIGH) to the right bit line.

Abstract: The present invention relates to a method for fabricating a memory device. According to this invention, because the trenches for the isolation structures are etched simultaneously as patterning the first conductive layer and the first dielectric layer, the formed isolation structures are self-aligned with the stacked gate structures, thus increasing the reliability for the memory device by avoiding misalignment problems.

Abstract: A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant and sandwiched between wide-band-gap insulators resulting in low leakage currents and high capacitance per unit area is achieved. The high-k layer increases the capacitance per unit area for next generation mixed-signal devices while the wide-band-gap insulators reduce leakage currents. In a second embodiment, a multilayer of different high-k materials is formed between the wide-band-gap insulators to substantially increase the capacitance per unit area. The layer materials and thicknesses are optimized to reduce the nonlinear capacitance dependence on voltage.

Abstract: An electrically programmable non-volatile memory cell is provided. A semiconductor substrate is prepared. A pair of spaced apart source/drain (S/D) regions is defined on the semiconductor substrate. The spaced apart S/D regions define a channel region in between. A first dielectric layer such as silicon dioxide is disposed on the S/D regions. An assistant gate is stacked on the first dielectric layer. The assistant gate has a top surface and sidewalls. A second dielectric layer comprising a charge-trapping layer is uniformly disposed on the top surface and sidewalls of the assistant gate and is also disposed on the channel region. The second dielectric layer provides a recessed trough between the S/D regions. A conductive gate material fills the recessed trough for controlling said channel region.

Abstract: A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant and sandwiched between wide-band-gap insulators resulting in low leakage currents and high capacitance per unit area is achieved. The high-k layer increases the capacitance per unit area for next generation mixed-signal devices while the wide-band-gap insulators reduce leakage currents. In a second embodiment, a multilayer of different high-k materials is formed between the wide-band-gap insulators to substantially increase the capacitance per unit area. The layer materials and thicknesses are optimized to reduce the nonlinear capacitance dependence on voltage.

Abstract: A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.

Abstract: A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.

Abstract: A method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper damascene process is described. A contact node is provided overlying a semiconductor substrate. An intermetal dielectric layer is deposited overlying the contact node. A damascene opening is formed through the intermetal dielectric layer to the contact node. A first metal layer is formed on the bottom and sidewalls of the damascene opening and overlying the intermetal dielectric layer. A first barrier metal layer is is deposited overlying the first metal layer. A dielectric layer is dpeosited overlying the first barrier metal layer. A second barrier metal layer is deposited overlying the dielectric layer. A second metal layer is formed overlying the second barrier metal layer and completely filling the damascene opening.

Abstract: A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.