Abstract: A high electron mobility transistor (HEMT) device including the following components is provided. A gate electrode is located on a barrier layer. A source electrode is located on the first side of the gate electrode. A drain electrode is located on the second side of the gate. A source field plate is connected to the source electrode. The source field plate includes first, second, and third field plate portions. The first field plate portion is connected to the source electrode and is located on the first side of the gate electrode. The second field plate portion is located on the second side of the gate electrode. The third field plate portion is connected to the end of the first field plate portion and the end of the second field plate portion. The source field plate has a first opening located directly above the gate electrode.

Abstract: A method of fabricating an embedded nonvolatile memory device is disclosed. A semiconductor substrate having thereon a fin body protruding from an isolation layer is provided. A charge storage layer crossing the fin body is formed. An inter-layer dielectric layer is deposited on the semiconductor substrate. The inter-layer dielectric layer is polished to expose a top surface of the charge storage layer. The charge storage layer is then recess etched and cut into separate charge storage structures. A high-k dielectric layer is formed on the charge storage structures. A word line is formed on the high-k dielectric layer.

Abstract: A method of fabricating a semiconductor device with fin-shaped structures includes respectively forming first fin-shaped structures in a first region and a second region of a semiconductor substrate, depositing a dielectric layer to completely cover the first fin-shaped structures, removing the first fin-shaped structures in the second region so as to form trenches in the dielectric layer, and performing an in-situ doping epitaxial growth process so as to respectively form second fin-shaped structures in the trenches.

Abstract: A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.

Abstract: A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.

Abstract: A method for fabricating a metal-oxide-semiconductor field-effect transistor includes the following steps. Firstly, a substrate is provided. A gate structure, a first spacer, a second spacer and a source/drain structure are formed over the substrate. The second spacer includes an inner layer and an outer layer. Then, a thinning process is performed to reduce the thickness of the second spacer, thereby retaining the inner layer of the second spacer. After a stress film is formed on the inner layer of the second spacer and the source/drain structure, an annealing process is performed. Afterwards, the stress film is removed.

Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.

Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.

Abstract: A method for fabricating a metal-oxide-semiconductor field-effect transistor includes the following steps. Firstly, a substrate is provided. A gate structure, a first spacer, a second spacer and a source/drain structure are formed over the substrate. The second spacer includes an inner layer and an outer layer. Then, a thinning process is performed to reduce the thickness of the second spacer, thereby retaining the inner layer of the second spacer. After a stress film is formed on the inner layer of the second spacer and the source/drain structure, an annealing process is performed. Afterwards, the stress film is removed.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.

Abstract: A method for fabricating a semiconductor device with enhanced channel stress is provided. The method includes the following steps. Firstly, a substrate is provided. Then, at least one source/drain region and a channel are formed in the substrate. A dummy gate is formed over the channel. A contact structure is formed over the source/drain region. After the contact structure is formed, the dummy gate is removed to form a trench.

Abstract: A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.

Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.

Abstract: A method for forming a metal-oxide-semiconductor (MOS) device includes at least steps of forming a pair of trenches in a substrate at both sides of a gate structure, filling the trenches with a silicon germanium layer by a selective epitaxy growth process, forming a cap layer on the silicon germanium layer by a selective growth process, and forming a pair of source/drain regions by performing an ion implantation process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Abstract: A method for forming a transistor having a metal gate is provided. A substrate is provided first. A transistor is formed on the substrate. The transistor includes a high-k gate dielectric layer, an oxygen containing dielectric layer disposed on the high-k gate dielectric layer, and a dummy gate disposed on the oxygen containing dielectric layer. Then, the dummy gate and the patterned gate dielectric layer are removed. Lastly, a metal gate is formed and the metal gate directly contacts the high-k gate oxide.