Abstract: A reference voltage generator circuit having a feedback circuit connected to an output branch. The circuit has a first branch, having a first current and a first voltage, a second branch, having a second current and a second voltage, and a third branch, having a third current and a third voltage. The circuit has an amplifier that couples the first voltage to the second voltage. The circuit also has a feedback circuit that couples the third voltage to at least one of the first or second voltages.

Abstract: A differential amplifier and a method thereof are described. The method, adopted by a differential amplifier, includes: generating first stage differential output signals based on input differential signals; providing, by a current source, a bias current with a desired quiescent current; biasing first and second control transistors with the bias current to generate first and second currents, respectively, wherein the first and second control transistors form a differential pair which receives first stage differential input signals; mirroring the first and second currents to first and second push transistors which are connected to first and second pull transistors in series, respectively; and biasing the first and second pull transistors with the mirrored first and second currents, respectively; wherein each pair of serial connected push and pull transistors are complimentary and the two pairs of push and pull transistors output second stage differential output signals.

Abstract: A signal demodulation apparatus includes: a clock generation device arranged to generate a clock signal according to an inputting modulation signal; and a demodulation device arranged to demodulate the inputting modulation signal to generate a demodulation signal according to the clock signal; wherein a signal edge of the clock signal substantially aligns to a turning point of the inputting modulation signal.

Abstract: A signal demodulation apparatus includes: a clock generation device arranged to generate a clock signal according to an inputting modulation signal; and a demodulation device arranged to demodulate the inputting modulation signal to generate a demodulation signal according to the clock signal; wherein a signal edge of the clock signal substantially aligns to a turning point of the inputting modulation signal.

Abstract: A differential amplifier and a method thereof are described. The method, adopted by a differential amplifier, includes: generating first stage differential output signals based on input differential signals; providing, by a current source, a bias current with a desired quiescent current; biasing first and second control transistors with the bias current to generate first and second currents, respectively, wherein the first and second control transistors form a differential pair which receives first stage differential input signals; mirroring the first and second currents to first and second push transistors which are connected to first and second pull transistors in series, respectively; and biasing the first and second pull transistors with the mirrored first and second currents, respectively; wherein each pair of serial connected push and pull transistors are complimentary and the two pairs of push and pull transistors output second stage differential output signals.

Abstract: A phase lock loop having a lock detector is provided. The lock detector is based on a replica charge pump and includes: a charge pump, a filter and a comparing circuit. The charge pump is arranged for providing an output according to a phase difference between an output signal and a reference signal. The filter is coupled to the charge pump, and is arranged for filtering the output of the charge pump to generate a filtered output voltage. The comparing circuit is coupled to the filter, and is arranged for comparing the filtered output voltage with a threshold setting to generate a lock indication signal to indicate whether the output signal is locked to the reference signal.

Abstract: A phase lock loop having a lock detector is provided. The lock detector is based on a replica charge pump and includes: a charge pump, a filter and a comparing circuit. The charge pump is arranged for providing an output according to a phase difference between an output signal and a reference signal. The filter is coupled to the charge pump, and is arranged for filtering the output of the charge pump to generate a filtered output voltage. The comparing circuit is coupled to the filter, and is arranged for comparing the filtered output voltage with a threshold setting to generate a lock indication signal to indicate whether the output signal is locked to the reference signal.

Abstract: A system is provided to perform non-recursive signal processing using a sampled data technique and a parallel network of switched-capacitor filters. The input analog signal is sampled in a time sequence manner at regular time intervals to obtain analog-valued samples. These samples are collected into data blocks that are assembled into a set of data blocks. The successive data blocks belonging to a set of data blocks partially overlap with the first data block. The non-recursive signal processing is performed on all of the data blocks of the set substantially simultaneously, using the parallel network to produce a processed analog output signal. Each individual processing path of the parallel network processes a specific data block of the set of data blocks. The number of parallel processing paths is the same as one plus the degree of the polynomial representing the desired or overall input/output equation characterizing the non-recursive signal processing.

Abstract: A level sensitive comparing device includes: a first comparator, a second comparator, and a determination circuit. The first comparator is arranged for comparing an input signal with a first reference level to generate a first comparison signal. The second comparator is arranged for comparing the input signal with a second reference level to generate a second comparison signal, wherein the second reference level is different from the first reference level. The determination circuit is coupled to the first comparator and the second comparator, and is arranged for determining whether the first comparison signal is allowed to appear at an output of the level sensitive comparing device according to at least the first comparison signal and the second comparison signal, wherein the determination circuit is composed of digital components only.

Abstract: A shock detector, such as for disk drives, which eliminates discrete external capacitors used in prior art devices. A first stage operational amplifier (without external capacitors) provides part of the gain required. This is followed by a second stage switched capacitor high pass filter (without external capacitors) that provides the remaining gain required while filtering out the DC offset of the first stage operational amplifier. In order to cover the range of frequencies expected without aliasing problems, two switched capacitor high pass filters in parallel are used, each designed with a different cut-off frequency.

Abstract: A scheme for enhancement of the power-supply ripple rejection for operational amplifiers (op-amps) and low-dropout (LDO) voltage regulators is described. The scheme adds calculated amounts of current derived from the power-supply ripple with the input differential pair current to cancel off the output ripple, improving the high-frequency power-supply ripple rejection without requiring a substantial redesign of the circuitry involved.

Abstract: To provide adequate compensation for a wide range of output loads, a low dropout (LDO) regulator has an amplifier, a pass transistor, a voltage divider, a compensation network, and a control circuit. The amplifier outputs a comparison result according to a reference signal and a feedback signal. The pass transistor generates an output current based on the comparison result of the amplifier. The voltage divider generates the feedback signal according to the output current. The compensation network couples the output of the pass transistor to a low-impedance node of the amplifier, and has a compensation capacitor and a variable resistor coupled to the compensation capacitor. The control circuit is coupled to the input of the pass transistor and to the variable resistor for controlling resistance of the variable resistor according to the output current of the pass transistor.

Abstract: A system is provided to perform non-recursive signal processing tasks using a sampled data technique and a network of switched-capacitor filters. The input analog signal is sampled in a time sequence manner at regular time intervals in order to obtain analog-valued samples. These samples are collected into data blocks and the data blocks are assembled into a set of data blocks. The successive data blocks belonging to a set of data blocks partially overlap with the first data block. The non-recursive signal processing is performed on all of the data blocks of the set substantially simultaneously, using a parallel network of switched capacitor filters, in order to produce a processed analog output signal. Each individual processing path of the parallel network of switched capacitor filters processes a specific data block of the set of data blocks.

Abstract: A scheme for enhancement of the power-supply ripple rejection for operational amplifiers (op-amps) and low-dropout (LDO) voltage regulators is described. The scheme adds calculated amounts of current derived from the power-supply ripple with the input differential pair current to cancel off the output ripple, improving the high-frequency power-supply ripple rejection without requiring a substantial redesign of the circuitry involved.

Abstract: A three-stage frequency-compensated operational amplifier includes a first-stage circuit, a second-stage circuit incorporated with a first compensation circuit, a third-stage circuit, and a second compensation circuit. The three-stage frequency-compensated operational amplifier functions as a two-stage operational amplifier at high frequencies, thereby capable of driving large capacitive loads with low power consumption.

Abstract: A driving amplifier circuit includes: a first driver for sourcing a load current to a load; a second driver for sinking the load current from the load; a first operational amplifier (op-amp) for driving the first driver; a second operational amplifier for driving the second driver; a first bias circuit for biasing the first driver; a second bias circuit for biasing the second driver; an enabling circuit for enabling either the first bias circuit or the second bias circuit according to a control signal; a digital control circuit for monitoring currents of the first driver and the second driver to generate the control signal; and an offset equalization circuit, coupled between an internal node of the first operational amplifier and an internal node of the second operational amplifier, for adjusting DC offset of at least one of the first operational amplifier and the second operational amplifier.

Abstract: An amplifier circuit includes a first stage to generate a first stage output based on a signal input and a control input. A second stage in communication with the first stage output and the control input. The second stage includes a first current source driver operable in a constant current source mode or a driver mode. The first current source driver operates in either the constant current source mode or the driver mode based on the signal input and the control input.

Abstract: To provide adequate compensation for a wide range of output loads, a low dropout (LDO) regulator has an amplifier, a pass transistor, a voltage divider, a compensation network, and a control circuit. The amplifier outputs a comparison result according to a reference signal and a feedback signal. The pass transistor generates an output current based on the comparison result of the amplifier. The voltage divider generates the feedback signal according to the output current. The compensation network couples the output of the pass transistor to a low-impedance node of the amplifier, and has a compensation capacitor and a variable resistor coupled to the compensation capacitor. The control circuit is coupled to the input of the pass transistor and to the variable resistor for controlling resistance of the variable resistor according to the output current of the pass transistor.

Abstract: A three-stage frequency-compensated operational amplifier includes a first-stage circuit, a second-stage circuit incorporated with a first compensation circuit, a third-stage circuit, and a second compensation circuit. The three-stage frequency-compensated operational amplifier functions as a two-stage operational amplifier at high frequencies, thereby capable of driving large capacitive loads with low power consumption.

Abstract: A driving amplifier circuit includes: a first driver for sourcing a load current to a load; a second driver for sinking the load current from the load; a first operational amplifier (op-amp) for driving the first driver; a second operational amplifier for driving the second driver; a first bias circuit for biasing the first driver; a second bias circuit for biasing the second driver; an enabling circuit for enabling either the first bias circuit or the second bias circuit according to a control signal; a digital control circuit for monitoring currents of the first driver and the second driver to generate the control signal; and an offset equalization circuit, coupled between an internal node of the first operational amplifier and an internal node of the second operational amplifier, for adjusting DC offset of at least one of the first operational amplifier and the second operational amplifier.