Abstract: A high frequency differential amplifier with a circuit topology which ensures that bias currents of the high transconductance differential transistors with minimum channel length are exactly equal, i.e., each differential transistor carries exactly half of the total current I0 of the differential amplifier. This is achieved by coupling each differential transistor via its own current source to the reference potential. To insure a good match between the current sources, the current source devices are made with long channel lengths. Impedances are coupled between the junctions of each differential transistor pair and its current source to insure good AC gain. For the variable gain differential amplifier the spread in the gain control characteristics is reduced by making the aspect ratio of the first pair of differential transistors larger than that of the second pair of differential transistors.

Abstract: A gain compensation circuit that compensates for variations in gain of a high gain, high frequency amplifier due to changes in mobility of transistor and resistor components of the amplifier. The gain compensation circuit includes a current adjustment circuit and a gain factor evaluation circuit. The current adjustment circuit modifies a bias current provided to each amplifier stage of a plurality of amplifier stages that make up the high gain, high frequency amplifier. The modification of the bias current adjusts the gain factor of the amplifier. The gain factor evaluation circuit is in communication with the current adjustment circuit to determine changes in the gain factor of the high gain, high frequency amplifier. From the determination, the gain factor evaluation circuit provides a compensation signal to the current adjustment circuit indicating a modification factor for the biasing current for each amplifier stage.

Abstract: A wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively and using CMOS technology, is comprised of a first and a second stage. The very low amplitude and phase matching errors have been achieved firstly by the use of capacitive means CD across the gate and source of the first stage MOS transistor M1 with a value equal to the drain to ground (reference potential) parasitic capacitance of the tail current source device for the first stage, and secondly by using equal valued capacitive means CF1, CF2 in the second stage and setting their values to be several (5-10) times more than the gate-drain parasitic capacitances of either of the differential transistors of the second stage.

Abstract: A buffer amplifier comprising a source follower-common drain circuit with a feedback path from the output of the drain follower to the input gate of the source follower. The feedback circuit is designed such that the output of the drain follower can be guaranteed to be at a voltage midway between the positive and the negative voltage supply of the circuit. This is the optimum operating point since it allows the largest signal swing. A small transconductance is realized by biasing the transistors of the feedback amplifier with very low currents; preferably by operating them in their weak inversion region. Feedback through the feedback amplifier is only present at DC (direct current) and at very low frequencies. This stabilizes the DC voltage at the drain of the common drain transistor, which, via an output capacitor, is also the output of the buffer amplifier.

Abstract: A stacked capacitor that has a large capacitance per unit area (Co), very low voltage coefficient (Kv), and an acceptable parasitic capacitance factor (Kp) is described that uses only one polysilicon layer. The stacked capacitor is formed at the surface of a semiconductor substrate of a first conductivity type. The stacked capacitor has a bottom plate that is formed by a lightly doped well diffused into the surface of the semiconductor substrate. The bottom plate also has a first plurality of interconnected conductive layers of a first conductive material disposed above and aligned with the well, whereby a first conductive layer of the first plurality of conductive layers is connected to the well by multiple contacts distributed over an area of the well.

Abstract: A method and system for designing a two-stage operational amplifier having low total harmonic distortion. The method begins with estimating a gain level of a second stage of the operational amplifier. Then a transconductance of the second stage is calculated. A unity gain frequency level for the first stage is calculated and from that the one kilohertz gain level of the first stage. The gain level at one kilohertz is then calculated and from this, the unity gain frequency for the operational amplifier is then calculated. A value of the compensation capacitor for said operational amplifier is calculated followed by calculating a transconductance of a first stage of the operational amplifier. The overall D.C. gain level and the output resistance of the first stage of the operational amplifier is then determined.

Abstract: A method and circuits are disclosed for an operational amplifier operating from a single cell 1.5 Volt supply which consumes very little power, and which can handle rail-to-rail input common mode and output signal swings. Low voltage and low power operation are made possible by biasing the CMOS transistors of the entire operational amplifier in the so called “sub-threshold” or “weak inversion” region of operation. This lowers VGSN and VGSP below VTN and VTP, and also lowers VDsat so that the operational amplifier can operate down to 0.9 Volt. The Class AB control circuit part of the operational amplifier can be applied to any conventional (normal biasing—other than weak inversion) low voltage Class AB output stage. The output stage of the operational amplifier is designed to source and sink more than 60 microAmperes of current into a 10 Kohm load while consuming only 4 micoramperes of current in the quiescent state.

Abstract: Methods and circuits are disclosed for low voltage (1.5 Volt and below) CMOS circuits, offering good transconductance and current driving capabilities. These goals are achieved by biasing CMOS transistors in the weak inversion region, by utilizing multiple unit-sized transistors with a fixed gate width to gate length ratio, and by maintaining a uniform threshold voltage of each unit-sized transistor. The required transistor size is obtained by parallel connection of several unit-sized transistors, such that `n` unit sized transistors carry the required current of `n` units. The methods and circuits disclosed eliminate deviation of the output current of current mirrors caused by threshold voltage mismatch. Disclosed are a current mirror and two typical amplifiers as examples of weak inversion design.

Abstract: A stacked capacitor that has a large capacitance per unit area (Co), very low voltage coefficient (Kv), and an acceptable parasitic capacitance factor (Kp) is described that uses only one polysilicon layer. The stacked capacitor is formed at the surface of a semiconductor substrate of a first conductivity type. The stacked capacitor has a bottom plate that is formed by a lightly doped well diffused into the surface of the semiconductor substrate. The bottom plate also has a first plurality of interconnected conductive layers of a first conductive material disposed above and aligned with the well, whereby a first conductive layer of the first plurality of conductive layers is connected to the well by multiple contacts distributed over an area of the well.

Abstract: A circuit and a method are disclosed which offer a solution for integrating a power-on-reset circuit that is realizable in a small space, consumes very little power, and works for practically any rate of rise of the power supply. These goals have been achieved by detecting, in a first section of the circuit, when the supply voltage reaches the threshold voltage V.sub.TP of a p-channel transistor, and activates power-on-reset by forcing that signal to logical zero (active). This first section detects next when the supply voltage reaches 2V.sub.TP and signals to a second section of the circuit to start charging a capacitor. The charging rate of the capacitor is controlled in such a way that its voltage lags behind the supply voltage, so that if the rise of the supply voltage is very fast, the duration T.sub.D of power-on-reset is long enough to insure complete resetting of the circuits it serves, such as digital memory elements, digital registers etc.

Abstract: In this invention a time constant tuning circuit is described in which a reference clock frequency is used to adjust the gm of a transconductor and as a result the time constant of the circuit. This is done by charging a capacitor to a voltage with the current output of a transconductor during a clock period and comparing the voltage charge with another voltage. The error voltage from the comparison is used to control the gm of the transconductor. Changing the clock period changes the gm required to charge the capacitor to a voltage to satisfy the comparison. Thus the filter time constants are directly proportional to the reference clock; and therefore, are independent of process variations. The time constants can be varied by varying the clock frequency and is achieved without the use of a PLL. The output the time constant tuning circuit can be used to tune the time constants of other gm-c filters using similar transconductors and capacitors.

Abstract: A circuit and a method are disclosed for a power start-up reset circuit which is self-timing and which can be fully integrated in a standard CMOS or BiCMOS process along with other digital circuits. The circuit provides a system reset signal which is issued only after all circuit have stabilized by making the issuance of this system reset signal dependent on an oscillator becoming stable and a subsequent count of a fixed number of system clock cycles derived from that oscillator.

Abstract: A fractional period delay circuit to delay a clocking signal by a non-integer fraction of the period of the clocking signal is disclosed. The fractional period delay circuit has a first delay line connected to a master timing signal to delay the master clock to form the first timing signal. The fractional period delay circuit has plurality of adjustable delay lines. Each adjustable delay line is connected to the master timing signal to delay the master timing A delay adjustment input will modify the delay of the adjustable delay circuit. The fractional period delay circuit further has a plurality of phase difference detectors connected to the output of the first delay line and to the output of one of the plurality of adjustable delay lines. The phase difference detector will create a difference signal indicating a difference in phase between the first timing signal and one of the delayed timing signals. A plurality of sequence timing signals are created in a is timing sequence generator.

Abstract: A circuit and a method are disclosed to provide a tristate input/output buffer which is compatible with 5 volt input signals, applied to its output node, while operating with a 3 volt power supply. This is achieved by inserting an extra p-channel transistor in series with the existing p-channel transistor. The extra p-channel transistor and its parasitic diode are wired so that they will not conduct, i.e. the extra transistor is off and the parasitic diode is back-biased, when a 5 volt input signal is applied to the output of the tristate input/output buffer. Two additional transistors are used to control the on/off state of the extra p-channel transistor.

Abstract: A clock waveform synthesizer that will create a timing signal that is a multiple of the frequency of an master clock is disclosed and has the capability to programmably adjust the rising edges and falling edges of the synthesized waveform within the period of the master clocks. The clock waveform synthesizer has a multi-tapped delay line. The multi-tapped delay line will create replications of the master clock that are incrementally delayed from the master clock to create a plurality of delay signals. A fraction of the plurality of delay signals will be the inputs to each of a plurality of multiplexers. A select port on each of the multiplexers will receive a select signal to choose one delay signal of the fraction of the plurality of delay signals. The one selected delay signals will be the input to the set terminals and reset terminals of a plurality of edge-triggered set/reset flip-flops.

Abstract: A circuit is disclosed for a complimentary metal oxide semiconductor (CMOS) operational amplifier output stage which can be connected easily to almost any input stage design and which can be coupled directly to that input stage. The circuit uses nine small transistors and two output transistors. The output transistors are connected in series between the power supply rails and the size of the two output transistors determines the current available to the load. The circuit of the invention can provide rail-to-rail output voltage swings and can drive a low ohm resistive load.

Abstract: A transmit amplifier for a telephone set without its own power supply has an LED with an anode connected to a first positive terminal of the telephone line and a circuit that determines the ratio between the line current and the line voltage. The LED is supplied with a constant current and this current is derived when the voltage across the terminals of the line becomes lower than a predetermined value.