Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

Abstract: A memory sub-system having a memory device with a plurality of cells and a processing device operatively coupled to the memory device, the processing device to perform the operations of: responsive to detecting a power off event, programming, to a predefined logical state, a dummy subset of the plurality of cells; responsive to detecting a power-up event, determining a voltage shift associated with the dummy subset of the plurality of cells; and identifying, based on the voltage shift, a voltage offset bin shift corresponding to a voltage offset bin associated with a specified subset of the plurality of cells.

Abstract: One or more trim values associated with a set of blocks of a memory device are set according to a representative number of program erase cycles (PECs) for the set of blocks. Each block in the set of blocks was programmed within at least one of a specified time window or a specified temperature range. Responsive to executing a program operation on a block of the set of blocks according to the one or more trim values, an indicator is set to reflect the one or more trim values used during the execution of the program operation. Responsive to receiving a request to perform a read operation directed to the block of the set of blocks, a read offset value corresponding to the indicator is determined. The read operation is performed using the read offset value.

Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Abstract: Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another.

Abstract: A variety of applications can include one or more memory devices having user data preloaded for the application prior to reflowing the memory devices on the system platform of the application. A touch-up data refresh method can be implemented to gain read window budget and to improve retention slope to protect the preload content to tolerate reflow to the system platform. Techniques for data preload can include programming preload data into targeted blocks until the targeted blocks are programmed with the preload data and re-programming the preload data over the programmed preload data in the targeted blocks in a same set of memory cells, without an erase between programming and re-programming the preload data. Variations of such techniques can be used to prepare a memory device with preload data followed by performing a reflow of the memory device to a structure for an application to which the memory device is implemented.

Abstract: A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.

Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The processing device is further to receive a second read command at a second time. The processing device is further to determine that the first read command and the second read command are directed to an at least partially same set of memory cells of the plurality of memory cells. The processing device is further to perform a media management operation with respect to the at least partially same set of memory cells.

Abstract: A system may include a memory device comprising a plurality of memory blocks, and a processing device to, responsive to receiving a request to read a memory block from the memory device, determine a time difference between a current time and a timestamp associated with the memory block, determine whether the time difference satisfies a first threshold increment criterion, responsive to determining that the time difference satisfies the first threshold increment criterion, increment a read counter associated with the memory block by a first increment value associated with the first threshold increment criterion, determine that the read counter associated with the memory block satisfies a threshold scan criterion, and responsive to determining that the read counter satisfies the threshold scan criterion, perform a media scan with respect to the memory block.

Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Abstract: An average number of program erase cycles (PECs) for a memory device is identified. A set of trims associated with the average number of PECs is identified. One or more write trims associated with the memory device are set according to the set of trims. A write command directed to the memory device is received. The write command is executed according to the one or more write trims.

Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.

Abstract: Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another.

Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.

Abstract: A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.

Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Abstract: A memory device may include a memory and a controller. The controller may be configured to receive a read command associated with a block of the memory. The controller may be configured to determine a block type associated with the block. The controller may be configured to identify, based on the block type, one or more read voltage offsets for a read operation associated with the block. The controller may be configured to perform the read operation based on the one or more read voltage offsets.

Abstract: Methods, systems, and devices for transient and stable state read operations of a memory device are described. A memory system may implement a read operation including a delay if a channel is at stable state, and may implement a read operation without a delay if the channel is in a transient state. Upon receiving a read command to a set of memory cells sharing the channel, the memory system may determine whether the channel is in a stable or transient state. If the channel is in a stable state, the memory system may perform a read operation including a delay between boosting the channel and driving respective word lines, such that the channel partially discharges prior to driving the word lines. If the channel is in a transient state, the memory system may perform a read operation without a delay between boosting the channel and driving the word lines.

Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.

Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.