Patents by Inventor Ugo Russo
Ugo Russo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11569255Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: May 7, 2021Date of Patent: January 31, 2023Assignee: Micron Technology, Inc.Inventors: Chris M. Carlson, Ugo Russo
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Publication number: 20230005553Abstract: Control logic in a memory device executes a first operation comprising a first set of programming pulses and a first set of program verify operations on a first portion of a first subset of memory cells to be programmed to identify a first start voltage level. A second set of programming pulses including at least one programming pulse having the first start voltage level is caused to be applied to program a second portion of the first subset of memory cells. A second operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second start voltage level.Type: ApplicationFiled: September 8, 2022Publication date: January 5, 2023Inventors: Lawrence Celso Miranda, Eric N. Lee, Tong Liu, Sheyang Ning, Cobie B. Loper, Ugo Russo
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Patent number: 11526277Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.Type: GrantFiled: January 25, 2021Date of Patent: December 13, 2022Assignee: Micron Technology, Inc.Inventors: Giuseppe Cariello, Mauro Luigi Sali, Stefano Falduti, Ugo Russo
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Patent number: 11462281Abstract: Control logic in a memory device identifies a first group of wordlines associated with a first subset of memory cells of a set of memory cells to be programmed. A first dynamic start voltage operation including a first set of programming pulses and a first set of program verify operations is executed on a first portion of the first subset of memory cells to identify a first dynamic start voltage level, the executing of the first dynamic start voltage operation includes causing the first set of programming pulses to be applied to at least a portion of the first group of wordlines. A second set of programming pulses including at least one programming pulse having the first dynamic start voltage level are caused to be applied to the first group of wordlines to program a second portion of the first subset of memory cells of the set of memory cells. A second group of wordlines associated with a second subset of memory cells to be programmed is identified.Type: GrantFiled: May 4, 2021Date of Patent: October 4, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Lawrence Celso Miranda, Eric N. Lee, Tong Liu, Sheyang Ning, Cobie B. Loper, Ugo Russo
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Publication number: 20220102378Abstract: A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.Type: ApplicationFiled: December 7, 2021Publication date: March 31, 2022Inventors: Ugo Russo, Chris M. Carlson
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Publication number: 20220037346Abstract: Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another.Type: ApplicationFiled: October 12, 2021Publication date: February 3, 2022Applicant: Micron Technology, Inc.Inventor: Ugo Russo
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Patent number: 11211399Abstract: A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.Type: GrantFiled: August 15, 2019Date of Patent: December 28, 2021Assignee: Micron Technology, Inc.Inventors: Ugo Russo, Chris M. Carlson
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Patent number: 11170826Abstract: Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another.Type: GrantFiled: March 5, 2020Date of Patent: November 9, 2021Assignee: Micron Technology, Inc.Inventor: Ugo Russo
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Publication number: 20210265365Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: May 7, 2021Publication date: August 26, 2021Inventors: Chris M. Carlson, Ugo Russo
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Patent number: 11037951Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: September 24, 2019Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Chris M. Carlson, Ugo Russo
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Publication number: 20210141530Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.Type: ApplicationFiled: January 25, 2021Publication date: May 13, 2021Inventors: Giuseppe Cariello, Mauro Luigi Sali, Stefano Falduti, Ugo Russo
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Publication number: 20210098067Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining a voltage level of a stepped sense operation that activates a memory cell of the memory during a programming operation for the memory cell, and determining a voltage level of a ramped sense operation that activates the memory cell during a read operation for the memory cell.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Ugo Russo, Violante Moschiano, William C. Filipiak, Andrea D'Alessandro
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Publication number: 20210050363Abstract: A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.Type: ApplicationFiled: August 15, 2019Publication date: February 18, 2021Inventors: Ugo Russo, Chris M. Carlson
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Patent number: 10901622Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.Type: GrantFiled: December 28, 2018Date of Patent: January 26, 2021Assignee: Micron Technology, Inc.Inventors: Giuseppe Cariello, Mauro Luigi Sali, Stefano Falduti, Ugo Russo
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Patent number: 10872670Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining a voltage level of a stepped sense operation that activates a memory cell of the memory during a programming operation for the memory cell, and determining a voltage level of a ramped sense operation that activates the memory cell during a read operation for the memory cell.Type: GrantFiled: December 17, 2018Date of Patent: December 22, 2020Assignee: Micron Technology, Inc.Inventors: Ugo Russo, Violante Moschiano, William C. Filipiak, Andrea D'Alessandro
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Publication number: 20200210067Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Giuseppe Cariello, Mauro Luigi Sali, Stefano Falduti, Ugo Russo
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Publication number: 20200202906Abstract: Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another.Type: ApplicationFiled: March 5, 2020Publication date: June 25, 2020Applicant: Micron Technology, Inc.Inventor: Ugo Russo
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Publication number: 20200194084Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining a voltage level of a stepped sense operation that activates a memory cell of the memory during a programming operation for the memory cell, and determining a voltage level of a ramped sense operation that activates the memory cell during a read operation for the memory cell.Type: ApplicationFiled: December 17, 2018Publication date: June 18, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Ugo Russo, Violante Moschiano, William C. Filipiak, Andrea D'Alessandro
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Patent number: 10658428Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.Type: GrantFiled: November 9, 2018Date of Patent: May 19, 2020Assignee: Micron Technology, Inc.Inventors: Ugo Russo, Andrea Redaelli, Giorgio Servalli
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Patent number: 10614862Abstract: An assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another.Type: GrantFiled: March 20, 2018Date of Patent: April 7, 2020Assignee: Micron Technology, Inc.Inventor: Ugo Russo