Patents by Inventor Uk Jang

Uk Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145474
    Abstract: A semiconductor device includes a substrate, a first active pattern disposed on the substrate, a second active pattern stacked on the first active pattern, a first gate structure extending to intersect the first active pattern and the second active pattern, a second gate structure spaced apart from the first gate structure and extending to intersect the first active pattern and the second active pattern, a first epitaxial pattern interposed between the first gate structure and the second gate structure, and connected to the first active pattern, a second epitaxial pattern interposed between the first gate structure and the second gate structure, and connected to the second active pattern, an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern, and a semiconductor film interposed between the insulating pattern and the second epitaxial pattern, the semiconductor film extending along a top surface of the insulating pattern.
    Type: Application
    Filed: May 9, 2023
    Publication date: May 2, 2024
    Inventors: Kyung ho KIM, Myung Il KANG, Sung Uk JANG, Kyung Hee CHO, Do Young CHOI
  • Patent number: 11973066
    Abstract: A light-emitting element includes a first end portion and a second end portion disposed in a length direction of the light-emitting element, a first electrode corresponding to the first end portion, a first semiconductor layer on the first electrode, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a second electrode on the second semiconductor layer and corresponding to the second end portion. The second electrode includes a first layer on the first semiconductor layer, and a second layer on the first layer. The first semiconductor layer includes a p-type semiconductor layer doped with a p-type dopant. The second semiconductor layer includes an n-type semiconductor layer doped with an n-type dopant. The first electrode is in ohmic contact with the first semiconductor layer. The second electrode is in ohmic contact with the second semiconductor layer.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: April 30, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyung Rae Cha, Dong Uk Kim, Sung Ae Jang, Ji Hyun Ham
  • Patent number: 11936219
    Abstract: The present invention relates to a battery protection circuit for accurately detecting and blocking overcurrent by overcharge and overdischarge by using a power management IC (PMIC) side sensing resistor provided in an external system and connected to a battery without a separate shunt resistor mounted in the battery, and an overcurrent blocking method using the same.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: March 19, 2024
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Won Jeon Jeong, Ji Uk Jang
  • Patent number: 11923145
    Abstract: A multilayer capacitor includes a body including a multilayer structure in which a plurality of dielectric layers are stacked in a first direction and a plurality of internal electrodes stacked with the dielectric layer interposed therebetween and external electrodes formed outside the body and connected to the internal electrodes. The body includes an active portion and a side margin portion covering the active portion and opposing each other in a second direction, and 1<A2/M1?1.5 and A2<A1 in which A1 is an average grain size of the dielectric layers in a central region of the active portion, A2 is an average grain size of the dielectric layers at an active boundary part of the active portion adjacent to the side margin portion, and M1 is an average grain size of the dielectric layers in a central region of the side margin portion.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: March 5, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Je Hee Lee, Seung In Baik, Ji Su Hong, Eun Ha Jang, Hyoung Uk Kim, Jae Sung Park
  • Patent number: 11922624
    Abstract: An apparatus for providing brain lesion information based on an image includes a magnetic resonance angiography (MRA) provider configured to provide an environment capable of displaying 3D time-of-flight magnetic resonance angiography (3D TOF MRA) using user input, a brain lesion input unit configured to generate and manage a brain lesion image, a maximum intensity projection (MIP) converter configured to configure MIP image data including at least one image frame corresponding to a projection position of the brain lesion image, a noise remover configured to remove noise of brain lesion information and to configure corrected MIP image data, from which the noise is removed, and an MRA reconfiguration unit configured to reconfigure a corrected brain lesion image by back-projecting the corrected MIP image data.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 5, 2024
    Assignee: JLK INC.
    Inventors: Won Tae Kim, Shin Uk Kang, Myung Jae Lee, Dong Min Kim, Jin Seong Jang
  • Patent number: 11915880
    Abstract: A multilayer electronic component includes a body including a plurality of dielectric layers, side margin portions disposed on the body, and external electrodes disposed on the body. The reliability of the multilayer electronic component is improved by controlling the contents of Si for each position of the dielectric layer and the side margin portion.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hee Sun Chun, Hyoung Uk Kim, Jae Sung Park, Hyeg Soon An, Ku Tak Lee, Eun Ha Jang
  • Patent number: 11916123
    Abstract: An integrated circuit device includes a substrate having source and drain recesses therein that are lined with respective silicon-germanium liners and filled with doped semiconductor source and drain regions. A stacked plurality of semiconductor channel layers are provided, which are separated vertically from each other within the substrate by corresponding buried insulated gate electrode regions that extend laterally between the silicon-germanium liners. An insulated gate electrode is provided on an uppermost one of the plurality of semiconductor channel layers. The silicon-germanium liners may be doped with carbon.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: February 27, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Dae Cho, Ki Hwan Kim, Sung Uk Jang, Su Jin Jung
  • Publication number: 20240063306
    Abstract: A semiconductor device is provided. The semiconductor comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern and in contact with the plurality of sheet patterns, and a gate structure on opposing sides of the source/drain pattern in a second direction different from the first direction, the gate structure including a gate electrode on the plurality of sheet patterns, wherein the source/drain pattern includes an epitaxial region that comprises a semiconductor material and a cavity region that is inside the epitaxial region and that is surrounded by the semiconductor material.
    Type: Application
    Filed: October 31, 2023
    Publication date: February 22, 2024
    Inventors: Su Jin JUNG, Ki Hwan KIM, Sung Uk JANG, Young Dae CHO
  • Patent number: 11901453
    Abstract: A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: February 13, 2024
    Inventors: Sung Uk Jang, Ki Hwan Kim, Su Jin Jung, Bong Soo Kim, Young Dae Cho
  • Publication number: 20240040879
    Abstract: An embodiment discloses a display panel and a display device including the same. The display panel includes a first display region in which a plurality of pixels are disposed, and a second display region including a plurality of pixel regions, in which a plurality of pixels are disposed, and a plurality of light-transmitting regions disposed between the plurality of pixel regions, wherein the second display region includes a plurality of first pixels disposed in the plurality of pixel regions, a plurality of second pixels disposed in the plurality of light-transmitting regions, and a plurality of first electrodes extending from the plurality of pixel regions to the plurality of light-transmitting regions to electrically connect the plurality of first pixels to the plurality of second pixels.
    Type: Application
    Filed: October 6, 2023
    Publication date: February 1, 2024
    Inventors: Hyung Uk Jang, Chul Nam
  • Patent number: 11884808
    Abstract: The present invention relates to a thermoplastic resin composition, which includes a first copolymer formed by polymerizing a monomer mixture of a (meth)acrylate-based monomer, a vinyl cyan-based monomer and a maleimide-based monomer, and having a refractive index of 1.5170 or less and a glass transition temperature of 115.0° C. or more; and a second copolymer formed by graft-copolymerizing an aromatic vinyl-based monomer and a vinyl cyan-based monomer onto an acrylic rubber polymer, and the thermoplastic resin composition according to the present invention has improved heat resistance, colorability and scratch resistance.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: January 30, 2024
    Assignee: LG CHEM, LTD.
    Inventors: Jung Tae Park, Dae Woo Lee, Jae Bum Seo, Gyu Sun Kim, Ji Uk Jang
  • Publication number: 20240002568
    Abstract: The present disclosure relates to a method of preparing a polymer including preparing a first polymer mixture by polymerizing while continuously adding a monomer mixture comprising a (meth)acrylate-based monomer, a vinyl aromatic monomer, and a first vinyl cyanide-based monomer to a first reactor; and preparing a second polymer mixture by polymerizing while continuously adding a second vinyl cyanide-based monomer and the first polymer mixture to a second reactor, wherein a starting time of the continuous addition of the second vinyl cyanide-based monomer and the first polymer mixture is a time when a polymerization conversion rate is 40.0 to 55.0%, and a weight ratio of the first vinyl cyanide-based monomer and the second vinyl cyanide-based monomer is 10:90 to 35:65.
    Type: Application
    Filed: August 17, 2022
    Publication date: January 4, 2024
    Applicant: LG CHEM, LTD.
    Inventors: Jae Bum SEO, Dae Woo LEE, Jung Tae PARK, Jung Rae LEE, Ji Uk JANG, Kyeong Soo SHIN
  • Patent number: 11843053
    Abstract: A semiconductor device is provided. The semiconductor comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern and in contact with the plurality of sheet patterns, and a gate structure on opposing sides of the source/drain pattern in a second direction different from the first direction, the gate structure including a gate electrode on the plurality of sheet patterns, wherein the source/drain pattern includes an epitaxial region that comprises a semiconductor material and a cavity region that is inside the epitaxial region and that is surrounded by the semiconductor material.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: December 12, 2023
    Inventors: Su Jin Jung, Ki Hwan Kim, Sung Uk Jang, Young Dae Cho
  • Patent number: 11818934
    Abstract: An embodiment discloses a display panel and a display device including the same. The display panel includes a first display region in which a plurality of pixels are disposed, and a second display region including a plurality of pixel regions, in which a plurality of pixels are disposed, and a plurality of light-transmitting regions disposed between the plurality of pixel regions, wherein the second display region includes a plurality of first pixels disposed in the plurality of pixel regions, a plurality of second pixels disposed in the plurality of light-transmitting regions, and a plurality of first electrodes extending from the plurality of pixel regions to the plurality of light-transmitting regions to electrically connect the plurality of first pixels to the plurality of second pixels.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: November 14, 2023
    Assignee: LG Display Co., Ltd.
    Inventors: Hyung Uk Jang, Chul Nam
  • Publication number: 20230307545
    Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure extending in a second direction and surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers, the source/drain region including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically in a third direction.
    Type: Application
    Filed: June 1, 2023
    Publication date: September 28, 2023
    Inventors: Sung Uk JANG, Young Dae CHO, Ki Hwan KIM, Su Jin JUNG
  • Patent number: 11728434
    Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: August 15, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok Hoon Kim, Dong Myoung Kim, Dong Suk Shin, Seung Hun Lee, Cho Eun Lee, Hyun Jung Lee, Sung Uk Jang, Edward Nam Kyu Cho, Min-Hee Choi
  • Publication number: 20230250210
    Abstract: The present disclosure relates to a method of preparing a graft polymer, which includes: performing primary continuous polymerization by adding a diene-based rubber polymer and an aromatic vinyl-based monomer to a first reactor; and performing secondary continuous polymerization by adding the polymerization product discharged from the first reactor, a maleimide-based monomer, and a vinyl cyanide-based monomer to a second reactor.
    Type: Application
    Filed: November 19, 2021
    Publication date: August 10, 2023
    Applicant: LG CHEM, LTD.
    Inventors: Ji Uk JANG, Dae Woo LEE, Jae Bum SEO, Jung Tae PARK, Jung Rae LEE
  • Patent number: 11708443
    Abstract: Provided is a method of preparing a graft copolymer, which includes: preparing a liquid maleimide-based monomer; preparing a reaction solution including a diene-based rubber polymer, an aromatic vinyl-based monomer, and a vinyl cyan-based monomer; and adding the liquid maleimide-based monomer and the reaction solution to a reactor and carrying out polymerization. According to the preparation method of the present invention, the amount of the maleimide-based monomer involved in the polymerization can be increased, and the color characteristics, glass transition temperature, and softening temperature of the graft copolymer are improved.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: July 25, 2023
    Assignee: LG CHEM, LTD.
    Inventors: Ji Uk Jang, Dae Woo Lee, Jae Bum Seo, Jung Tae Park, Gyu Sun Kim
  • Publication number: 20230208162
    Abstract: The present invention relates to a battery protection circuit and a method for protecting the battery protection circuit in which instead of connecting the charge/discharge FET on the current path between the battery and the external system, when an abnormal condition occurs in the battery, the 0V voltage of the battery cell is transmitted to the external system through the disconnection of the voltage sensing line to cut off the abnormal current of the battery in the external system.
    Type: Application
    Filed: August 20, 2021
    Publication date: June 29, 2023
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventor: Ji Uk JANG
  • Patent number: 11670716
    Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure extending in a second direction and surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers, the source/drain region including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically in a third direction.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: June 6, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Uk Jang, Young Dae Cho, Ki Hwan Kim, Su Jin Jung