Abstract: A phase locked loop is disclosed comprising: a phase detector, a loop filter, a frequency controller oscillator and a lock detector. The phase detector is operable in a bang-bang mode to provide a binary phase error signal indicating whether there is a positive or negative phase difference between a reference signal and a feedback signal. The loop filter is configured to provide a control signal derived from the binary phase error signal. The frequency controlled oscillator is configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal. The lock/unlock detector is configured to determine a lock/unlock state of the phase locked loop, the lock/unlock state derived from a duty cycle and/or spectral content of the binary phase error signal.

Abstract: An all digital phase locked loop system for tracking a variable frequency input signal and method of operation are described. The ADPLL system includes a digital phase locked loop, including a digitally controlled oscillator, and a model of the digitally controller oscillator. The model represents the behaviour of the digitally controlled oscillator as a function of frequency and has a model input arranged to receive a signal indicating a current target frequency. The model is configured to output at least one control signal to control the frequency of the digitally controlled oscillator to be closer to the current target frequency. The digital phase locked loop is configured to control the digitally controlled oscillator to reduce any difference between the frequency of the digitally controlled oscillator and the current target frequency arising from any deviation of the model of the digitally controlled oscillator from the digitally controlled oscillator.

Abstract: A phase locked loop is disclosed comprising: a phase detector, loop filter and a frequency controlled oscillator. The phase detector is configured to determine a phase difference between a reference signal and a feedback signal. The loop filter is configured to perform a filtering operation on a signal derived from the phase difference and to provide a control signal. The frequency controlled oscillator is configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal. The phase locked loop further comprises a lock detector, including: a phase lock detector configured to receive a first signal from the phase locked loop, and to derive a phase lock signal from the first signal; a frequency lock detector configured to receive a second signal from the phase locked loop, and to derive a frequency lock signal from the second signal.

Abstract: A phase locked loop, comprising: a phase detector configured to determine a phase difference between a reference signal and a feedback signal; a loop filter configured to perform a filtering operation on a signal derived from the phase difference, and to provide a control signal; a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal; wherein a low-pass filter is provided between the phase detector and the loop filter and/or between the loop filter and the frequency controlled oscillator to reduce quantization noise from the phase detector.

Abstract: A phase locked loop is disclosed comprising: a phase detector, loop filter and a frequency controlled oscillator. The phase detector is configured to determine a phase difference between a reference signal and a feedback signal. The loop filter is configured to perform a filtering operation on a signal derived from the phase difference and to provide a control signal. The frequency controlled oscillator is configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal. The phase locked loop further comprises a lock detector, including: a phase lock detector configured to receive a first signal from the phase locked loop, and to derive a phase lock signal from the first signal; a frequency lock detector configured to receive a second signal from the phase locked loop, and to derive a frequency lock signal from the second signal.

Abstract: Settling time may be reduced or eliminated for a phase-locked loop (ADPLL). An oscillator model provides proper settings that are applied to compensate both the frequency response and the phase response. A hardware device may include a Digital Controlled Oscillator (DCO); and a DCO model device with a processor, wherein the processor is configured to calculate a frequency for the DCO by searching for the frequency based upon operational parameters of the DCO, compare the calculated frequency to a measured frequency, and compensate, based upon the comparison, an ADPLL to decrease a settling time.

Abstract: Settling time may be reduced or eliminated for a phase-locked loop (ADPLL). An oscillator model provides proper settings that are applied to compensate both the frequency response and the phase response. A hardware device may include a Digital Controlled Oscillator (DCO); and a DCO model device with a processor, wherein the processor is configured to calculate a frequency for the DCO by searching for the frequency based upon operational parameters of the DCO, compare the calculated frequency to a measured frequency, and compensate, based upon the comparison, an ADPLL to decrease a settling time.

Abstract: A method for driving a sigma delta modulator, a sigma delta modulator comprising at least one integrator device and one quantizer device, and a readable medium having a computer program stored thereon for performing the method are described. The method comprises setting a sigma delta modulator to an irrational operation mode. The method comprises monitoring at least one output signal of the sigma delta modulator. The method comprises resetting the sigma delta modulator to the irrational operation mode depending on the monitored output signal.

Abstract: The present application relates to a method for driving a sigma delta modulator. The present application relates also to a sigma delta modulator comprising at least one integrator device and one quantizer device and it relates to a readable medium having a computer program stored thereon for performing said method. The method comprises setting a sigma delta modulator to an irrational operation mode. The method comprises monitoring at least one output signal of the sigma delta modulator. The method comprises resetting the sigma delta modulator to the irrational operation mode depending on the monitored output signal.

Abstract: In order to further develop a circuit arrangement (100; 102; 104; 106) and a method of locking onto and/or processing data, in particular audio, television and/or video data, by means of at least one phase locked loop (40), wherein phase information is detected by means of at least one phase detector (44), in particular following the arrival of at least one rising edge and/or falling edge of at least one analog input signal (50; 50), at least one increment (24) is determined by means of at least one loop filter (30), to which the output signal (56) which is output by the phase detector (44) is fed, and at least one ramp oscillator (46) is fed the increment (24) which is output by the loop filter (30), such that inter alia the circuit arrangement (100; 102; 104; 106).

Abstract: In order to further develop a circuit arrangement (100; 102; 104; 106) and a method of locking onto and/or processing data, in particular audio, T[ele]V[ision] and/or video data, by means of at least one phase locked loop (40), wherein phase information is detected by means of at least one phase detector (44), in particular following the arrival of at least one rising edge and/or falling edge of at least one analog input signal (50; 50), at least one increment (24) is determined by means of at least one loop filter (30), to which the output signal (56) which is output by the phase detector (44) is fed, and at least one ramp oscillator (46) is fed the increment (24) which is output by the loop filter (30), such that inter alia the circuit arrangement (100; 102; 104; 106) and the method for operating the same can be readily adapted to various requirements, it is proposed that the phase locked loop (40) is essentially digital, wherein the input signal (50; 50), in particular the phase of the input signal (50; 50

Abstract: In order to further develop a circuit arrangement (100), in particular to a phase-locked loop for sub-clock or sub-pixel accurate phase-measurement and phase-generation, as well as a corresponding method in such way that no clock multiplier phase-locked loop is to be provided behind the time-to-digital converter and that neither an analog delay line nor a signal divider unit is to be provided between the digital ramp oscillator or discrete time oscillator and the digital-to-time converter, wherein less analog circuitry is susceptible for noise and for ground bounce in the digital environment, it is proposed to provide at least one phase measurement unit (10);—at least one loop filter unit (40; 40?) being provided with at least one output signal (delta-phi) of at least one phase detector unit (30); at least one digital ramp oscillator unit or discrete time oscillator unit (50; 50?) being provided with at least one output signal, in particular with at least one increment (inc), of the loop filter unit (40; 40?)

Abstract: In order to further develop a circuit arrangement (100), in particular to a phase-locked loop for sub-clock or sub-pixel accurate phase-measurement and phase-generation, as well as a corresponding method in such way that no clock multiplier phase-locked loop is to be provided behind the time-to-digital converter and that neither an analog delay line nor a signal divider unit is to be provided between the digital ramp oscillator or discrete time oscillator and the digital-to-time converter, wherein less analog circuitry is susceptible for noise and for ground bounce in the digital environment, it is proposed to provide at least one phase measurement unit (10);—at least one loop filter unit (40; 40?) being provided with at least one output signal (delta-phi) of at least one phase detector unit (30); at least one digital ramp oscillator unit or discrete time oscillator unit (50; 50?) being provided with at least one output signal, in particular with at least one increment (inc), of the loop filter unit (40; 40?)

Abstract: The invention relates to an arrangement for generating a decoder clock signal for decoding a data signal which is available together with a clock signal and a data word signal signalizing data words, both of which signals may each have different frequencies. The arrangement comprises a phase control circuit (1) which receives the clock signal and supplies the decoder clock signal from its output, and which comprises at least one adjustable divider (14) which is preferably arranged at the input of the phase control circuit (1) and whose division ratio is adjustable.

Abstract: The invention relates to an arrangement for generating a decoder clock signal for decoding a data signal which is available together with a clock signal and a data word signal signalizing data words, both of which signals may each have different frequencies. The arrangement comprises a phase control circuit (1) which receives the clock signal and supplies the decoder clock signal from its output, and which comprises at least one adjustable divider (14) which is preferably arranged at the input of the phase control circuit (1) and whose division ratio is adjustable.