Patents by Inventor Umberto Siciliani
Umberto Siciliani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11550717Abstract: Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.Type: GrantFiled: August 22, 2019Date of Patent: January 10, 2023Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Andrea Giovanni Xotta, Umberto Siciliani, Luca DeSantis, Michele Incarnati
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Publication number: 20220405002Abstract: A system includes a memory array, a thermometer, and control logic, operatively coupled with the memory array and the thermometer, to perform operations including causing the thermometer to obtain a first temperature result, monitoring a time since obtaining the first temperature result, determining whether the time satisfies a threshold time condition, in response to determining that the time satisfies the threshold time condition, causing the thermometer to obtain a second temperature result from an automatic temperature reading, determining a difference between the second temperature result and a previously stored temperature result, and filtering the second temperature result based on the difference to obtain a new stored temperature result.Type: ApplicationFiled: November 29, 2021Publication date: December 22, 2022Inventors: Agostino Macerola, Michele Piccardi, Umberto Siciliani, Tommaso Vali, Enrico Favaro
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Publication number: 20220405013Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.Type: ApplicationFiled: January 31, 2022Publication date: December 22, 2022Inventors: Andrea Giovanni Xotta, Guido Luciano Rizzo, Umberto Siciliani, Tommaso Vali, Luca De Santis, Walter Di Francesco
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Publication number: 20220405182Abstract: A system includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing, during chip initialization, a first attempt of a chip initialization process to be performed based on a first configuration. The first configuration includes a first set of control settings for reading a block of the memory array during the first attempt. The operations further include determining that the first attempt has failed, and, in response to determining that the first attempt has failed, causing an automatic chip initialization retry process to be performed. Causing the automatic chip initialization retry process to be performed includes causing a second attempt of the chip initialization process to be performed using a second configuration. The second configuration includes a second set of control settings different from the first set of control settings for reading the block during the second attempt.Type: ApplicationFiled: January 25, 2022Publication date: December 22, 2022Inventors: Umberto Siciliani, Domenico Monteleone
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Publication number: 20220406388Abstract: Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.Type: ApplicationFiled: May 4, 2022Publication date: December 22, 2022Inventors: Umberto Siciliani, Tao Liu, Ting Luo, Dionisio Minopoli, Giuseppe D'Eliseo, Giuseppe Ferrari, Walter Di'Francesco, Antonino Pollio, Luigi Esposito, Anna Scalesse, Allison J. Olson, Anna Chiara Siviero
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Publication number: 20220342823Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a plurality of cache read commands requesting first data from the memory array spread across the plurality of memory planes and receives, from the requestor, a cache read context switch command and a snap read command requesting second data from one of the plurality of memory planes of the memory array. Responsive to receiving the cache read context switch command, the control logic suspends processing of the plurality of cache read commands and processes the snap read command to read the second data from the memory array and return the second data to the requestor.Type: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Inventors: Giuseppe D'Eliseo, Anna Scalesse, Umberto Siciliani, Carminantonio Manganelli
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Publication number: 20220208273Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation; and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.Type: ApplicationFiled: July 22, 2021Publication date: June 30, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Umberto Siciliani, Floriano Montemurro, Eric N. Lee, Dheeraj Srinivasan
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Publication number: 20220206712Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform a program operation and in response to the command to perform the program operation, begin execution of the program operation. The controller might be further configured to while executing the program operation, receive a command to perform a read operation; in response to the command to perform the read operation, suspend the execution of the program operation; and with the execution of the program operation suspended, execute the read operation.Type: ApplicationFiled: July 22, 2021Publication date: June 30, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Umberto Siciliani, Floriano Montemurro
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Publication number: 20220137856Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a first request to perform a first memory access operation on the memory array and initiates the first memory access operation on the memory array. Prior to completion of the first memory access operation, the control logic receives, from the requestor, a second request to suspend performance of the first memory access operation and causes the memory device to enter a suspend state, wherein the first memory access operation is suspended during the suspend state. The control logic further receives, from the requestor, a third request to perform a dynamic single-level cell (SLC) program operation on the memory array while the memory device is in the suspend state and initiates the dynamic SLC program operation on the memory array.Type: ApplicationFiled: October 29, 2020Publication date: May 5, 2022Inventor: Umberto Siciliani
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Publication number: 20220050685Abstract: Memory systems and memory control methods are described.Type: ApplicationFiled: October 27, 2021Publication date: February 17, 2022Applicant: Micron Technology, Inc.Inventors: Umberto Siciliani, Tommaso Vali, Walter Di-Francesco, Violante Moschiano, Andrea Smaniotto
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Patent number: 11163572Abstract: Memory systems and memory control methods are described.Type: GrantFiled: February 4, 2014Date of Patent: November 2, 2021Assignee: Micron Technology, Inc.Inventors: Umberto Siciliani, Tommaso Vali, Walter Di-Francesco, Violante Moschiano, Andrea Smaniotto
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Patent number: 10922220Abstract: Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can receive a page of data. The memory controller can segment the page of data into a group of data segments. The memory controller can program the group of data segments to memory cells in the plurality of memory cells that are associated with an inhibit tile group (ITG). The group of data segments for the page of data can be programmed using all bits included in each of the memory cells associated with the ITG.Type: GrantFiled: July 1, 2017Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: Umberto Siciliani, Giulio Giuseppe Marotta, Tommaso Vali, Luca De Santis, Agostino Macerola, Violante Moshciano, Luigi Pilolli, Giovanni Santin, Michele Incarnati
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Patent number: 10585606Abstract: Apparatuses and methods for configuring a memory device using configuration commands are provided. A method can include executing a first command while the memory device is in a ready state to configure the memory device to a particular mode and executing a second command to perform a first operation while the memory device is in the particular mode.Type: GrantFiled: August 15, 2019Date of Patent: March 10, 2020Assignee: Micron Technology, Inc.Inventors: Umberto Siciliani, Anna Chiara Siviero, Andrea Smaniotto
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Publication number: 20190377675Abstract: Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.Type: ApplicationFiled: August 22, 2019Publication date: December 12, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Tommaso Vali, Andrea Giovanni Xotta, Umberto Siciliani, Luca DeSantis, Michele Incarnati
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Publication number: 20190369889Abstract: Apparatuses and methods for configuring a memory device using configuration commands are provided. One example method can include executing a first command while the memory device is in a ready state to configure the memory device to a particular mode and executing a second command to perform a first operation while the memory device is in the particular mode.Type: ApplicationFiled: August 15, 2019Publication date: December 5, 2019Inventors: Umberto Siciliani, Anna Chiara Siviero, Andrea Smaniotto
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Patent number: 10402319Abstract: Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.Type: GrantFiled: July 25, 2014Date of Patent: September 3, 2019Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Andrea Giovanni Xotta, Umberto Siciliani, Luca DeSantis, Michele Incarnati
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Patent number: 10387060Abstract: Apparatuses and methods for configuring a memory device using configuration commands are provided. A method can include executing a first command while the memory device is in a ready state to configure the memory device to a particular mode and executing a second command to perform a first operation while the memory device is in the particular mode.Type: GrantFiled: March 29, 2018Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventors: Umberto Siciliani, Anna Chiara Siviero, Andrea Smaniotto
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Publication number: 20190004938Abstract: Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can receive a page of data. The memory controller can segment the page of data into a group of data segments. The memory controller can program the group of data segments to memory cells in the plurality of memory cells that are associated with an inhibit tile group (ITG). The group of data segments for the page of data can be programmed using all bits included in each of the memory cells associated with the ITG.Type: ApplicationFiled: July 1, 2017Publication date: January 3, 2019Applicant: Intel CorporationInventors: Umberto Siciliani, Giulio Giuseppe Marotta, Tommaso Vali, Luca De Santis, Agostino Macerola, Violante Moshciano, Luigi Pilolli, Giovanni Santin, Michele Incarnati
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Publication number: 20180217773Abstract: Apparatuses and methods for configuring a memory device using configuration commands are provided. One example method can include executing a first command while the memory device is in a ready state to configure the memory device to a particular mode and executing a second command to perform a first operation while the memory device is in the particular mode.Type: ApplicationFiled: March 29, 2018Publication date: August 2, 2018Inventors: Umberto Siciliani, Anna Chiara Siviero, Andrea Smaniotto
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Patent number: 10037809Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.Type: GrantFiled: October 2, 2017Date of Patent: July 31, 2018Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani