Patents by Inventor Umesh K
Umesh K has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12001315Abstract: Various embodiments for customizing a dynamic navigation system are described herein. An embodiment operates by receiving a request from a support user device for debug access to an application. A predetermined time period for which to provision a set of computing resources is identified and the set of computing resources are provisioned for a pod on a server. Both a first container including access to a new instance of the application and a second container providing access to a debugger program are generated for the pod. Upon determining that the predetermined time period has expired, access to the provisioned set of computing resources of the pod is revoked, and the provisioned set of computing resources to be made available for other processes of the server.Type: GrantFiled: February 9, 2022Date of Patent: June 4, 2024Assignee: SAP SEInventors: Umesh K, Christian Weiss, Chuanyu Wang, Mayank Gupta, Gaurav Prabakar, Jovin Jijo, Anirudh Prasad, Zehao Huang
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Patent number: 11973138Abstract: Described herein are lateral III-N (e.g., GaN) devices having a III-N depleting layer. A circuit includes a depletion-mode transistor with a source connected to a drain of an enhancement-mode transistor. The gate of the depletion-mode transistor and the gate of the enhancement-mode transistor are biased at zero volts, and the drain of the depletion-mode transistor is biased at positive voltage to block a current in a forward direction. Then, the bias of the gate of the enhancement-mode transistor is changed to a first voltage greater than the threshold voltage of the enhancement-mode transistor and a first current is allowed to flow through the channel in a forward direction. Then, the bias of the gate of the depletion-mode transistor is changed to a second voltage and a second current is allowed to flow through the channel in a forward direction where the second current is greater than the first current.Type: GrantFiled: January 28, 2022Date of Patent: April 30, 2024Assignee: Transphorm Technology, Inc.Inventors: Geetak Gupta, Umesh Mishra, Davide Bisi, Rakesh K. Lal, David Michael Rhodes
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Publication number: 20240063340Abstract: The present disclosure describes porous GaN layers and/or compliant substrates used to enable relaxation of previously strained top layers and the deposition of relaxed or partially relaxed on top. Relaxed In GaN layers are fabricated without generation of crystal defects, which can serve as base layers for high performance long wavelength light emitting devices (LEDs, lasers) solar cells, or strain engineered transistors. Similarly, relaxed AlGaN layers can serve as base layers for high performance short wavelength UV light emitting devices (LEDs, lasers) solar cells, or wide bandgap transistors.Type: ApplicationFiled: September 10, 2020Publication date: February 22, 2024Applicants: The Regents of the University of California, The Regents of the University of CaliforniaInventors: Stacia Keller, Umesh K. Mishra, Shubhra Pasayat, Chirag Gupta
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Patent number: 11829278Abstract: A method for secure debugging in a multitenant cloud environment where an application server maintains a host application shared by multiple tenant users can be implemented. The method can receive a request from a tenant user to debug the host application associated with a tenant user, and responsive to the request, deploy an application runtime environment comprising an application container encapsulating the host application associated with the tenant user and a debugger container encapsulating a debugging software running on the application server. The method can set at least a breakpoint in source code of the host application through a user interface of the debugging software, run the host application associated with the tenant user in the application runtime environment, and evaluate an expression entered through the user interface of the debugging software after the host application associated with the tenant user hits the breakpoint.Type: GrantFiled: December 16, 2021Date of Patent: November 28, 2023Assignee: SAP SEInventors: Umesh K, Jovin Jijo, Anirudh Prasad, Mohit V Gadkari, Christian Weiss
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Publication number: 20230134277Abstract: A method for secure debugging in a multitenant cloud environment where an application server maintains a host application shared by multiple tenant users can be implemented. The method can receive a request from a tenant user to debug the host application associated with a tenant user, and responsive to the request, deploy an application runtime environment comprising an application container encapsulating the host application associated with the tenant user and a debugger container encapsulating a debugging software running on the application server. The method can set at least a breakpoint in source code of the host application through a user interface of the debugging software, run the host application associated with the tenant user in the application runtime environment, and evaluate an expression entered through the user interface of the debugging software after the host application associated with the tenant user hits the breakpoint.Type: ApplicationFiled: December 16, 2021Publication date: May 4, 2023Applicant: SAP SEInventors: Umesh K, Jovin Jijo, Anirudh Prasad, Mohit V. Gadkari, Christian Weiss
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Publication number: 20230140208Abstract: Various embodiments for customizing a dynamic navigation system are described herein. An embodiment operates by receiving a request from a support user device for debug access to an application. A predetermined time period for which to provision a set of computing resources is identified and the set of computing resources are provisioned for a pod on a server. Both a first container including access to a new instance of the application and a second container providing access to a debugger program are generated for the pod. Upon determining that the predetermined time period has expired, access to the provisioned set of computing resources of the pod is revoked, and the provisioned set of computing resources to be made available for other processes of the server.Type: ApplicationFiled: February 9, 2022Publication date: May 4, 2023Inventors: Umesh K, Christian WEISS, Chuanyu WANG, Mayank GUPTA, Gaurav PRABAKAR, Jovin JIJO, Anirudh PRASAD, Zehao HUANG
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Patent number: 11594625Abstract: Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.Type: GrantFiled: February 26, 2020Date of Patent: February 28, 2023Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Matthew Guidry, Stacia Keller, Umesh K. Mishra, Brian Romanczyk, Xun Zheng
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Patent number: 11588096Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.Type: GrantFiled: April 11, 2017Date of Patent: February 21, 2023Assignee: The Regents of the University of CaliforniaInventors: Yuuki Enatsu, Chirag Gupta, Stacia Keller, Umesh K. Mishra, Anchal Agarwal
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Publication number: 20220399475Abstract: A substrate comprising a III-N base layer comprising a first portion and a second portion, the first portion of the III-N base layer having a first natural lattice constant and a first dislocation density; and a first III-N layer having a second natural lattice constant and a second dislocation density on the III-N base layer, the first III-N layer having a thickness greater than 10 nm. An indium fractional composition of the first III-N layer is greater than 0.1; the second natural lattice constant is at least 1% greater than the first natural lattice constant; a strain-induced lattice constant of the first III-N layer is greater than 1.0055 times the first natural lattice constant; and the second dislocation density is less than 1.5 times the first dislocation density.Type: ApplicationFiled: January 14, 2022Publication date: December 15, 2022Applicant: The Regents of the University of CaliforniaInventors: Kamruzzaman Khan, Elaheh Ahmadi, Stacia Keller, Christian Wurm, Umesh K. Mishra
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Publication number: 20220223429Abstract: N-polar transistor structures have relied on the use of dry etch processes that use plasmas generated from gaseous species to remove III-N layers as commercially viable wet etchants do not exist. The present disclosure reports on methods for the fabrication of N-polar III-N transistors using wet etches along with transistor structures that are enabled by the availability of wet-etches.Type: ApplicationFiled: June 18, 2021Publication date: July 14, 2022Applicant: The Regents of the University of CaliforniaInventors: Brian Romanczyk, Emmanuel Kayede, Wenjian Liu, Islam Sayed, Umesh K. Mishra
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Publication number: 20220102580Abstract: A method for fabricating a device, as well as the device itself, which includes growing a bonding layer on a first wafer or substrate, wherein the bonding layer includes at least partially relaxed features; and then bonding a second wafer or substrate to the features in on the first wafer or substrate, to cap and contact the features with separately grown material.Type: ApplicationFiled: January 16, 2020Publication date: March 31, 2022Applicant: The Regents of the University of CaliforniaInventors: Caroline E. Reilly, Umesh K. Mishra, Stacia Keller, Steven P. DenBaars
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Publication number: 20210399121Abstract: Derivative cancellation techniques have been used to linearize transistors using multiple discreet devices. However at frequencies approaching and in the mm-wave regime the use of individual devices no longer works due to the parasitics associated with combining the devices. In this invention device structures are described which apply the derivative cancellation technique in a single device thus removing the detrimental impact of combining. In one example, an N-polar transistor structure includes a channel; a cap structure comprising a plurality of cap layers on or above the channel; a source contact and a drain contact to the channel; and a castellated, stepped, or varying pattern formed in the cap layers so that gate metal deposited on the pattern forms at least two different threshold voltages and current combines in the ohmic region with essentially zero parasitic inductance.Type: ApplicationFiled: June 21, 2021Publication date: December 23, 2021Applicant: The Regents of the University of CaliforniaInventors: Brian Romanczyk, Umesh K. Mishra, Pawana Shrestha, Matthew Guidry, James Buckwalter, Stacia Keller, Rohit Reddy Karnaty
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Publication number: 20210399096Abstract: Strain is used to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition.Type: ApplicationFiled: November 7, 2019Publication date: December 23, 2021Applicant: The Regents of the University of CaliforniaInventors: Umesh K. Mishra, Stacia Keller, Elaheh Ahmadi, Chirag Gupta, Yusuke Tsukada
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Patent number: 11101379Abstract: A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As illustrated herein, a thin InGaN layer introduced in the channel increases the carrier density, reduces the electric field in the channel, and increases the carrier mobility. The dependence of p on InGaN thickness (tInGaN) and indium composition (xIn) was investigated for different channel thicknesses. With optimized tInGaN and xIn, significant improvements in electron mobility were observed. For a 6 nm channel HEMT, the electron mobility increased from 606 to 1141 cm2/(V·s) when the 6 nm thick pure GaN channel was replaced by the 4 nm GaN/2 nm In0.1Ga0.9N composite channel.Type: GrantFiled: November 16, 2017Date of Patent: August 24, 2021Assignee: THEREGENIS OF THE UNIVERSITY OF CALIFORNIAInventors: Brian Romanczyk, Haoran Li, Elaheh Ahmadi, Steven Wienecke, Matthew Guidry, Xun Zheng, Stacia Keller, Umesh K. Mishra
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Publication number: 20210150476Abstract: A system includes receiving, via a first user interface, a selection of a user interface field related to a business object, retrieving, from a metadata repository, modeling content of the business object, generating a second user interface including the modeling content retrieved from the metadata repository, and identifying metadata of the business object that corresponds to the user interface field by directly assessing the modeling content via the second user interface.Type: ApplicationFiled: November 18, 2019Publication date: May 20, 2021Inventors: Stefan Resag, Umesh K, Hemant Mangal
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Publication number: 20200273974Abstract: Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.Type: ApplicationFiled: February 26, 2020Publication date: August 27, 2020Applicant: The Regents of the University of CaliforniaInventors: Matthew Guidry, Stacia Keller, Umesh K. Mishra, Brian Romanczyk, Xun Zheng
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Patent number: 10529892Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.Type: GrantFiled: September 7, 2017Date of Patent: January 7, 2020Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, Japan Science and Technology AgencyInventors: Robert M. Farrell, Jr., Troy J. Baker, Arpan Chakraborty, Benjamin A. Haskell, P. Morgan Pattison, Rajat Sharma, Umesh K. Mishra, Steven P. DenBaars, James S. Speck, Shuji Nakamura
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Publication number: 20190348532Abstract: A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As illustrated herein, a thin InGaN layer introduced in the channel increases the carrier density, reduces the electric field in the channel, and increases the carrier mobility. The dependence of p on InGaN thickness (tInGaN) and indium composition (xIn) was investigated for different channel thicknesses. With optimized tInGaN and xIn, significant improvements in electron mobility were observed. For a 6 nm channel HEMT, the electron mobility increased from 606 to 1141 cm2/(V·s) when the 6 nm thick pure GaN channel was replaced by the 4 nm GaN/2 nm In0.1Ga0.9N composite channel.Type: ApplicationFiled: November 16, 2017Publication date: November 14, 2019Applicant: The Regents of the University of CaliforniaInventors: Brian Romanczyk, Haoran Li, Elaheh Ahmadi, Steven Wienecke, Matthew Guidry, Xun Zheng, Stacia Keller, Umesh K. Mishra
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Publication number: 20190181329Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.Type: ApplicationFiled: April 11, 2017Publication date: June 13, 2019Inventors: Yuuki Enatsu, Chirag Gupta, Stacia Keller, Umesh K. Mishra, Anchal Agarwal
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Patent number: 10312361Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.Type: GrantFiled: November 4, 2016Date of Patent: June 4, 2019Assignee: The Regents of the University of CaliforniaInventors: Srabanti Chowdhury, Jeonghee Kim, Chirag Gupta, Stacia Keller, Silvia H. Chan, Umesh K. Mishra