Patents by Inventor Umesh K

Umesh K has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12230678
    Abstract: The disclosure describes the use of strain to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: February 18, 2025
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Umesh K. Mishra, Stacia Keller, Elaheh Ahmadi, Chirag Gupta, Yusuke Tsukada
  • Patent number: 12211955
    Abstract: A substrate comprising a III-N base layer comprising a first portion and a second portion, the first portion of the III-N base layer having a first natural lattice constant and a first dislocation density; and a first III-N layer having a second natural lattice constant and a second dislocation density on the III-N base layer, the first III-N layer having a thickness greater than 10 nm. An indium fractional composition of the first III-N layer is greater than 0.1; the second natural lattice constant is at least 1% greater than the first natural lattice constant; a strain-induced lattice constant of the first III-N layer is greater than 1.0055 times the first natural lattice constant; and the second dislocation density is less than 1.5 times the first dislocation density.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: January 28, 2025
    Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Kamruzzaman Khan, Elaheh Ahmadi, Stacia Keller, Christian Wurm, Umesh K. Mishra
  • Patent number: 12159929
    Abstract: An electronic device including a substrate a group III-V layer on or above the substrate, wherein the III-V layer has an in-plane lattice constant that is greater than that of gallium nitride or wherein the III-V layer is at least partially relaxed; and an active region including a coherently strained group III-V channel layer on or above the III-V layer; wherein electron mobility in the channel layer is increased by the strain. Structures with an in-plane lattice constant that is smaller than that of gallium nitride are used for increasing the hole mobility by strain.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: December 3, 2024
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Stacia Keller, Umesh K. Mishra
  • Patent number: 12135634
    Abstract: A computer system may receive a user input associated with a source code file via a first user interface displayed a first computing device, where the source code file comprising source code of a software application. The computer system may then obtain a tracing configuration based on the user input, where the tracing configuration comprises a line number of the source code and a variable within the source code. Next, the computer system may set a breakpoint in the source code at the line number using the tracing configuration, and then trace the variable during execution of the source code, where the tracing comprises determining a value of the variable using the breakpoint in the source code and creating a call stack based on the execution of the source code. The computer system may then store the value of the variable and the call stack in a log.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: November 5, 2024
    Assignee: SAP SE
    Inventors: Umesh K, Jovin Jijo
  • Publication number: 20240289256
    Abstract: A computer system may receive a user input associated with a source code file via a first user interface displayed a first computing device, where the source code file comprising source code of a software application. The computer system may then obtain a tracing configuration based on the user input, where the tracing configuration comprises a line number of the source code and a variable within the source code. Next, the computer system may set a breakpoint in the source code at the line number using the tracing configuration, and then trace the variable during execution of the source code, where the tracing comprises determining a value of the variable using the breakpoint in the source code and creating a call stack based on the execution of the source code. The computer system may then store the value of the variable and the call stack in a log.
    Type: Application
    Filed: February 27, 2023
    Publication date: August 29, 2024
    Inventors: Umesh K, Jovin Jijo
  • Patent number: 12001315
    Abstract: Various embodiments for customizing a dynamic navigation system are described herein. An embodiment operates by receiving a request from a support user device for debug access to an application. A predetermined time period for which to provision a set of computing resources is identified and the set of computing resources are provisioned for a pod on a server. Both a first container including access to a new instance of the application and a second container providing access to a debugger program are generated for the pod. Upon determining that the predetermined time period has expired, access to the provisioned set of computing resources of the pod is revoked, and the provisioned set of computing resources to be made available for other processes of the server.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: June 4, 2024
    Assignee: SAP SE
    Inventors: Umesh K, Christian Weiss, Chuanyu Wang, Mayank Gupta, Gaurav Prabakar, Jovin Jijo, Anirudh Prasad, Zehao Huang
  • Publication number: 20240063340
    Abstract: The present disclosure describes porous GaN layers and/or compliant substrates used to enable relaxation of previously strained top layers and the deposition of relaxed or partially relaxed on top. Relaxed In GaN layers are fabricated without generation of crystal defects, which can serve as base layers for high performance long wavelength light emitting devices (LEDs, lasers) solar cells, or strain engineered transistors. Similarly, relaxed AlGaN layers can serve as base layers for high performance short wavelength UV light emitting devices (LEDs, lasers) solar cells, or wide bandgap transistors.
    Type: Application
    Filed: September 10, 2020
    Publication date: February 22, 2024
    Applicants: The Regents of the University of California, The Regents of the University of California
    Inventors: Stacia Keller, Umesh K. Mishra, Shubhra Pasayat, Chirag Gupta
  • Patent number: 11829278
    Abstract: A method for secure debugging in a multitenant cloud environment where an application server maintains a host application shared by multiple tenant users can be implemented. The method can receive a request from a tenant user to debug the host application associated with a tenant user, and responsive to the request, deploy an application runtime environment comprising an application container encapsulating the host application associated with the tenant user and a debugger container encapsulating a debugging software running on the application server. The method can set at least a breakpoint in source code of the host application through a user interface of the debugging software, run the host application associated with the tenant user in the application runtime environment, and evaluate an expression entered through the user interface of the debugging software after the host application associated with the tenant user hits the breakpoint.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: November 28, 2023
    Assignee: SAP SE
    Inventors: Umesh K, Jovin Jijo, Anirudh Prasad, Mohit V Gadkari, Christian Weiss
  • Publication number: 20230134277
    Abstract: A method for secure debugging in a multitenant cloud environment where an application server maintains a host application shared by multiple tenant users can be implemented. The method can receive a request from a tenant user to debug the host application associated with a tenant user, and responsive to the request, deploy an application runtime environment comprising an application container encapsulating the host application associated with the tenant user and a debugger container encapsulating a debugging software running on the application server. The method can set at least a breakpoint in source code of the host application through a user interface of the debugging software, run the host application associated with the tenant user in the application runtime environment, and evaluate an expression entered through the user interface of the debugging software after the host application associated with the tenant user hits the breakpoint.
    Type: Application
    Filed: December 16, 2021
    Publication date: May 4, 2023
    Applicant: SAP SE
    Inventors: Umesh K, Jovin Jijo, Anirudh Prasad, Mohit V. Gadkari, Christian Weiss
  • Publication number: 20230140208
    Abstract: Various embodiments for customizing a dynamic navigation system are described herein. An embodiment operates by receiving a request from a support user device for debug access to an application. A predetermined time period for which to provision a set of computing resources is identified and the set of computing resources are provisioned for a pod on a server. Both a first container including access to a new instance of the application and a second container providing access to a debugger program are generated for the pod. Upon determining that the predetermined time period has expired, access to the provisioned set of computing resources of the pod is revoked, and the provisioned set of computing resources to be made available for other processes of the server.
    Type: Application
    Filed: February 9, 2022
    Publication date: May 4, 2023
    Inventors: Umesh K, Christian WEISS, Chuanyu WANG, Mayank GUPTA, Gaurav PRABAKAR, Jovin JIJO, Anirudh PRASAD, Zehao HUANG
  • Patent number: 11594625
    Abstract: Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: February 28, 2023
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Matthew Guidry, Stacia Keller, Umesh K. Mishra, Brian Romanczyk, Xun Zheng
  • Patent number: 11588096
    Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: February 21, 2023
    Assignee: The Regents of the University of California
    Inventors: Yuuki Enatsu, Chirag Gupta, Stacia Keller, Umesh K. Mishra, Anchal Agarwal
  • Publication number: 20220399475
    Abstract: A substrate comprising a III-N base layer comprising a first portion and a second portion, the first portion of the III-N base layer having a first natural lattice constant and a first dislocation density; and a first III-N layer having a second natural lattice constant and a second dislocation density on the III-N base layer, the first III-N layer having a thickness greater than 10 nm. An indium fractional composition of the first III-N layer is greater than 0.1; the second natural lattice constant is at least 1% greater than the first natural lattice constant; a strain-induced lattice constant of the first III-N layer is greater than 1.0055 times the first natural lattice constant; and the second dislocation density is less than 1.5 times the first dislocation density.
    Type: Application
    Filed: January 14, 2022
    Publication date: December 15, 2022
    Applicant: The Regents of the University of California
    Inventors: Kamruzzaman Khan, Elaheh Ahmadi, Stacia Keller, Christian Wurm, Umesh K. Mishra
  • Publication number: 20220223429
    Abstract: N-polar transistor structures have relied on the use of dry etch processes that use plasmas generated from gaseous species to remove III-N layers as commercially viable wet etchants do not exist. The present disclosure reports on methods for the fabrication of N-polar III-N transistors using wet etches along with transistor structures that are enabled by the availability of wet-etches.
    Type: Application
    Filed: June 18, 2021
    Publication date: July 14, 2022
    Applicant: The Regents of the University of California
    Inventors: Brian Romanczyk, Emmanuel Kayede, Wenjian Liu, Islam Sayed, Umesh K. Mishra
  • Publication number: 20220102580
    Abstract: A method for fabricating a device, as well as the device itself, which includes growing a bonding layer on a first wafer or substrate, wherein the bonding layer includes at least partially relaxed features; and then bonding a second wafer or substrate to the features in on the first wafer or substrate, to cap and contact the features with separately grown material.
    Type: Application
    Filed: January 16, 2020
    Publication date: March 31, 2022
    Applicant: The Regents of the University of California
    Inventors: Caroline E. Reilly, Umesh K. Mishra, Stacia Keller, Steven P. DenBaars
  • Publication number: 20210399121
    Abstract: Derivative cancellation techniques have been used to linearize transistors using multiple discreet devices. However at frequencies approaching and in the mm-wave regime the use of individual devices no longer works due to the parasitics associated with combining the devices. In this invention device structures are described which apply the derivative cancellation technique in a single device thus removing the detrimental impact of combining. In one example, an N-polar transistor structure includes a channel; a cap structure comprising a plurality of cap layers on or above the channel; a source contact and a drain contact to the channel; and a castellated, stepped, or varying pattern formed in the cap layers so that gate metal deposited on the pattern forms at least two different threshold voltages and current combines in the ohmic region with essentially zero parasitic inductance.
    Type: Application
    Filed: June 21, 2021
    Publication date: December 23, 2021
    Applicant: The Regents of the University of California
    Inventors: Brian Romanczyk, Umesh K. Mishra, Pawana Shrestha, Matthew Guidry, James Buckwalter, Stacia Keller, Rohit Reddy Karnaty
  • Publication number: 20210399096
    Abstract: Strain is used to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition.
    Type: Application
    Filed: November 7, 2019
    Publication date: December 23, 2021
    Applicant: The Regents of the University of California
    Inventors: Umesh K. Mishra, Stacia Keller, Elaheh Ahmadi, Chirag Gupta, Yusuke Tsukada
  • Patent number: 11101379
    Abstract: A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As illustrated herein, a thin InGaN layer introduced in the channel increases the carrier density, reduces the electric field in the channel, and increases the carrier mobility. The dependence of p on InGaN thickness (tInGaN) and indium composition (xIn) was investigated for different channel thicknesses. With optimized tInGaN and xIn, significant improvements in electron mobility were observed. For a 6 nm channel HEMT, the electron mobility increased from 606 to 1141 cm2/(V·s) when the 6 nm thick pure GaN channel was replaced by the 4 nm GaN/2 nm In0.1Ga0.9N composite channel.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: August 24, 2021
    Assignee: THEREGENIS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Brian Romanczyk, Haoran Li, Elaheh Ahmadi, Steven Wienecke, Matthew Guidry, Xun Zheng, Stacia Keller, Umesh K. Mishra
  • Publication number: 20210150476
    Abstract: A system includes receiving, via a first user interface, a selection of a user interface field related to a business object, retrieving, from a metadata repository, modeling content of the business object, generating a second user interface including the modeling content retrieved from the metadata repository, and identifying metadata of the business object that corresponds to the user interface field by directly assessing the modeling content via the second user interface.
    Type: Application
    Filed: November 18, 2019
    Publication date: May 20, 2021
    Inventors: Stefan Resag, Umesh K, Hemant Mangal
  • Publication number: 20200273974
    Abstract: Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 27, 2020
    Applicant: The Regents of the University of California
    Inventors: Matthew Guidry, Stacia Keller, Umesh K. Mishra, Brian Romanczyk, Xun Zheng