Patents by Inventor Umesh K. Mishra

Umesh K. Mishra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200273974
    Abstract: Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 27, 2020
    Applicant: The Regents of the University of California
    Inventors: Matthew Guidry, Stacia Keller, Umesh K. Mishra, Brian Romanczyk, Xun Zheng
  • Patent number: 10529892
    Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: January 7, 2020
    Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, Japan Science and Technology Agency
    Inventors: Robert M. Farrell, Jr., Troy J. Baker, Arpan Chakraborty, Benjamin A. Haskell, P. Morgan Pattison, Rajat Sharma, Umesh K. Mishra, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Publication number: 20190348532
    Abstract: A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As illustrated herein, a thin InGaN layer introduced in the channel increases the carrier density, reduces the electric field in the channel, and increases the carrier mobility. The dependence of p on InGaN thickness (tInGaN) and indium composition (xIn) was investigated for different channel thicknesses. With optimized tInGaN and xIn, significant improvements in electron mobility were observed. For a 6 nm channel HEMT, the electron mobility increased from 606 to 1141 cm2/(V·s) when the 6 nm thick pure GaN channel was replaced by the 4 nm GaN/2 nm In0.1Ga0.9N composite channel.
    Type: Application
    Filed: November 16, 2017
    Publication date: November 14, 2019
    Applicant: The Regents of the University of California
    Inventors: Brian Romanczyk, Haoran Li, Elaheh Ahmadi, Steven Wienecke, Matthew Guidry, Xun Zheng, Stacia Keller, Umesh K. Mishra
  • Publication number: 20190181329
    Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.
    Type: Application
    Filed: April 11, 2017
    Publication date: June 13, 2019
    Inventors: Yuuki Enatsu, Chirag Gupta, Stacia Keller, Umesh K. Mishra, Anchal Agarwal
  • Patent number: 10312361
    Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: June 4, 2019
    Assignee: The Regents of the University of California
    Inventors: Srabanti Chowdhury, Jeonghee Kim, Chirag Gupta, Stacia Keller, Silvia H. Chan, Umesh K. Mishra
  • Publication number: 20180013035
    Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.
    Type: Application
    Filed: September 7, 2017
    Publication date: January 11, 2018
    Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, Japan Science and Technology Agency
    Inventors: Robert M. Farrell, JR., Troy J. Baker, Arpan Chakraborty, Benjamin A. Haskell, P. Morgan Pattison, Rajat Sharma, Umesh K. Mishra, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Patent number: 9793435
    Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 17, 2017
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Robert M. Farrell, Jr., Troy J. Baker, Arpan Chakraborty, Benjamin A. Haskell, P. Morgan Pattison, Rajat Sharma, Umesh K. Mishra, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Patent number: 9691712
    Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: June 27, 2017
    Assignee: The Regents of the University of California
    Inventors: Hugues Marchand, Brendan J. Moran, Umesh K. Mishra, James S. Speck
  • Publication number: 20170125574
    Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.
    Type: Application
    Filed: November 4, 2016
    Publication date: May 4, 2017
    Applicants: The Regents of the University of Calfornia, Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Srabanti Chowdhury, Jeonghee Kim, Chirag Gupta, Stacia Keller, Silvia H. Chan, Umesh K. Mishra
  • Patent number: 9590088
    Abstract: A current aperture vertical electron transistor (CAVET) with ammonia (NH3) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: March 7, 2017
    Assignee: The Regents of the University of California
    Inventors: Srabanti Chowdhury, Ramya Yeluri, Christophe Hurni, Umesh K. Mishra, Ilan Ben-Yaacov
  • Patent number: 9496353
    Abstract: A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: November 15, 2016
    Assignees: The Regents of the University of California, Cree, Inc.
    Inventors: Alessandro Chini, Umesh K. Mishra, Primit Parikh, Yifeng Wu
  • Publication number: 20160163846
    Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.
    Type: Application
    Filed: January 28, 2016
    Publication date: June 9, 2016
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Xiang Liu, Umesh K. Mishra, Stacia Keller, Jeonghee Kim, Matthew Laurent, Jing Lu, Ramya Yeluri, Silvia H. Chan
  • Publication number: 20160079738
    Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 17, 2016
    Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, Japan Science and Technology Agency
    Inventors: Robert M. Farrell, Troy J. Baker, Arpan Chakraborty, Benjamin A. Haskell, P. Morgan Pattison, Rajat Sharma, Umesh K. Mishra, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Patent number: 9281183
    Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: March 8, 2016
    Assignee: The Regents of the University of California
    Inventors: Xiang Liu, Umesh K. Mishra, Stacia Keller, Jeonghee Kim, Matthew Laurent, Jing Lu, Ramya Yeluri, Silvia H. Chan
  • Patent number: 9263423
    Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistance with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: February 16, 2016
    Assignee: The Regents of the University of California
    Inventors: Arpan Chakraborty, Likun Shen, Umesh K. Mishra
  • Patent number: 9231376
    Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: January 5, 2016
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Robert M. Farrell, Jr., Troy J. Baker, Arpan Chakraborty, Benjamin A. Haskell, P. Morgan Pattison, Rajat Sharma, Umesh K. Mishra, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Publication number: 20150294960
    Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistance with improved current spreading and improved heat-sinking Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.
    Type: Application
    Filed: June 3, 2015
    Publication date: October 15, 2015
    Applicant: The Regents of the University of California
    Inventors: Arpan Chakraborty, Likun Shen, Umesh K. Mishra
  • Patent number: 9129977
    Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: September 8, 2015
    Assignee: The Regents of the University of California
    Inventors: Hugues Marchand, Brendan J. Moran, Umesh K. Mishra, James S. Speck
  • Publication number: 20150200286
    Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.
    Type: Application
    Filed: January 15, 2015
    Publication date: July 16, 2015
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Xiang Liu, Umesh K. Mishra, Stacia Keller, Jeonghee Kim, Matthew Laurent, Jing Lu, Ramya Yeluri, Silvia H. Chan
  • Patent number: 9076927
    Abstract: A method of fabricating a heterostructure device, including (a) obtaining a first layer or substrate; (b) growing a second layer on the first layer or substrate; and (c) forming the second layer that is at least partially relaxed wherein (1) the first layer and the second layer have the same lattice structure but different lattice constants, (2) the first layer and the second layer form a heterojunction, and (3) the heterojunction forms an active area of a device or serves as a pseudo-substrate for the device.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: July 7, 2015
    Assignee: The Regents of the University of California
    Inventors: Stacia Keller, Carl J. Neufeld, Umesh K. Mishra, Steven P. DenBaars