Abstract: The present invention allows the growth of InGaN with greater compositions of Indium than traditionally available now, which pushes LED and LD wavelengths into the yellow and red portions of the color spectrum. The ability to grow with Indium at higher temperatures leads to a higher quality AlInGaN. This also allows for novel polarization-based band structure designs to create more efficient devices. Additionally, it allows the fabrication of p-GaN layers with increased conductivity, which improves device performance.

Abstract: A flip-chip integrated circuit and method for fabricating the integrated circuit are disclosed. A method according to the invention comprises forming a plurality of active semiconductor devices on a wafer and separating the active semiconductor devices. Passive components and interconnections are formed on a surface of a circuit substrate and at least one conductive via is formed through the circuit substrate. At least one of the active semiconductor devices is flip-chip mounted on the circuit substrate with at least one of the bonding pads in electrical contact with one of the conductive vias. A flip-chip integrated circuit according to the present invention comprises a circuit substrate having passive components and interconnections on one surface and can have a conductive via through it. An active semiconductor device is flip-chip mounted on the circuit substrate, one of the at least one vias is in contact with one of the at least one the device's terminals.

Abstract: A method for producing a wafer bonded structure between (Al, In, Ga)N and Zn(S,Se). A highly reflective and conductive distributed Bragg reflector (DBR) for relatively short optical wave lengths can be fabricated using Zn(S,Se) and MgS/(Zn, Cd)Se materials. Using wafer bonding techniques, these high-quality DBR structures can be combined with a GaN-based optical device structure.

Abstract: A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11{overscore (2)}0) a-plane GaN layers are grown on an r-plane (1{overscore (1)}02) sapphire substrate using MOCVD. These non-polar (11{overscore (2)}0) a-plane GaN layers comprise templates for producing non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices.

Abstract: A flip-chip integrated circuit includes a circuit substrate having electronic components. The circuit substrate typically includes GaAs or Si. Another substrate can include Group III nitride based active semiconductor devices. This substrate typically includes SiC and can be separated to provide individual nitride devices. After separation, one or more of the Group III devices can be flip-chip mounted onto the circuit substrate. The electronic components on the circuit substrate can be coupled to the nitride devices using conductive interconnects and/or vias.

Abstract: A flip-chip integrated circuit and method for fabricating the integrated circuit are disclosed. A method according to the invention comprises forming a plurality of active semiconductor devices on a wafer and separating the active semiconductor devices. Passive components and interconnections are formed on a surface of a circuit substrate and at least one conductive via is formed through the circuit substrate. At least one of the active semiconductor devices is flip-chip mounted on the circuit substrate with at least one of the bonding pads in electrical contact with one of the conductive vias. A flip-chip integrated circuit according to the present invention comprises a circuit substrate having passive components and interconnections on one surface and can have a conductive via through it. An active semiconductor device is flip-chip mounted on the circuit substrate, one of the at least one vias is in contact with one of the at least one the device's terminals.

Abstract: Growth of doped gallium nitride, especially p-type gallium nitride, without using post-growth processing is achieved by eliminating hydrogen containing molecules from the growth process before cooling down the substrate. Rapid cooling of the substrate with nitrogen gas prevents the reaction of p-type dopant atoms with hydrogen, and the use of the nitrogen gas also keeps the nitrogen intact within the crystalline structure.

Abstract: The gate voltage breakdown of an integrated circuit field effect transistor, expecially a compound semiconductor metal semiconductor field effect transistor (MESFET) and high electron mobility transistor (HEMT) is dramatically increased by forming an electron trap layer on the surface of the device, under the gate contact and extending beyond the gate contact towards the drain contact. The electron trap layer is preferably a high resistivity lattice matched monocrystalline layer having at least 10.sup.18 traps per cubic centimeter. For gallium arsenide based transistors, the electron trap layer is preferably formed by low temperature molecular beam epitaxy (MBE) of gallium and arsenic fluxes, to produce a monocrystalline gallium arsenide layer having 1% excess arsenic. For indium phosphide based transistors, the electron trap layer is preferably formed by low temperature MBE of aluminum, indium and arsenic fluxes to produce a monocrystalline aluminum indium arsenide layer having 1% excess arsenic.

Abstract: A channel layer, donor layer, Schottky layer, and cap layer are formed on a substrate. A source and drain are formed on the cap layer. A gate is formed on the cap layer, or at the bottom of a recess which is formed through the cap layer and partially extends into the Schottky layer. The donor and Schottky layers are formed of a semiconductive material which includes an oxidizable component such as aluminum. A passivation or stop layer of a lattice-matched, non-oxidizable material is formed underlying the source, drain, and gate, and sealingly overlying the donor layer. The stop layer may be formed between the Schottky layer and the donor layer, or constitute a superlattice in combination with the Schottky layer consisting of alternating stop and Schottky sublayers. Alternatively, the stop layer may sealingly overlie the Schottky layer, and further constitute the cap layer.

Abstract: The gate voltage breakdown of an integrated circuit field effect transistor, especially a compound semiconductor metal semiconductor field effect transistor (MESFET) and high electron mobility transistor (HEMT) is dramatically increased by forming an electron trap layer on the surface of the device, under the gate contact and extending beyond the gate contact towards the drain contact. The electron trap layer is preferably a high resisitivity lattice matched monocrystalline layer having at least 10.sup.18 traps per cubic centimeter. For gallium arsenide based transistors, the electron trap layer is preferably formed by low temperature molecular beam epitaxy (MBE) of gallium and arsenic fluxes, to produce a monocrystalline gallium arsenide layer having 1% excess arsenic. For indium phosphide based transistors, the electron trap layer is preferably formed by low temperature MBE of aluminum, indium and arsenic fluxes to produce a monocrystalline aluminum indium arsenide layer having 1% excess arsenic.

Abstract: A planar doped barrier region of semiconductor material is coupled to a vacuum or gaseous region to provide electron emission from the planar doped barrier region into the vacuum or gaseous region. When a voltage is applied across the planar doped barrier region electrons flow from one end of the region to another. This flow results in the emission of electrons if the work function of the emission surface is less than the bandgap of the semiconductor material. The device of the present invention can be used as a vacuum microelectronic emitter, a vacuum microelectronic transistor, light source, klystron, or travelling wave tube.

Abstract: A generally T-shaped gate is formed by electron beam irradiation of a multilevel resist structure on a substrate. The resist structure has an upper layer which is more sensitive to the electron beam than a lower layer thereof. A generally T-shaped opening is formed in the resist structure by etching of the irradiated areas. An electrically conductive metal is deposited to fill the opening and thereby form a T-shaped gate on the substrate. After the resist layer structure and metal deposited thereon is removed, a masking layer is formed on the substrate around the gate, having an opening therethrough which is aligned with and wider than the cross section of the gate, and defining first and second lateral spacings between opposite extremities of the cross section and adjacent edges of the opening. Deposition of an electrically conductive metal forms source and drain metallizations on the substrate on areas underlying the first and lateral spacings respectively.