Patents by Inventor Un Sang LEE
Un Sang LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961574Abstract: A memory device includes a memory block including memory cells to which a program voltage is applied through a word line. The memory device also includes a peripheral circuit configured to perform a verify operation of comparing threshold voltages of the memory cells with a verify voltage on each of a plurality of program levels. The memory device further includes a control logic circuit configured to control the peripheral circuit to apply a plurality of blind voltages related to a target level among the plurality of program levels to the word line, and determine a start time point of a verify operation corresponding to a next program level of the target level using the number of fail bits for each of the plurality of blind voltages.Type: GrantFiled: January 13, 2022Date of Patent: April 16, 2024Assignee: SK hynix Inc.Inventors: June Young Choi, Un Sang Lee
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Patent number: 11810623Abstract: Disclosed is an operating method of a controller for controlling an operation of a semiconductor memory device including a plurality of memory cells. In the operating method of the controller, program data to be stored in a selected page of the semiconductor memory device is generated, and the semiconductor memory device is controlled to program the program data in the selected page. Bit data at a predetermined position in the program data is data for allowing a threshold voltage of a corresponding memory cell to maintain an erase state.Type: GrantFiled: August 5, 2021Date of Patent: November 7, 2023Assignee: SK hynix Inc.Inventors: Un Sang Lee, Moon Sik Seo
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Publication number: 20230046005Abstract: A memory device includes a memory block including memory cells to which a program voltage is applied through a word line. The memory device also includes a peripheral circuit configured to perform a verify operation of comparing threshold voltages of the memory cells with a verify voltage on each of a plurality of program levels. The memory device further includes a control logic circuit configured to control the peripheral circuit to apply a plurality of blind voltages related to a target level among the plurality of program levels to the word line, and determine a start time point of a verify operation corresponding to a next program level of the target level using the number of fail bits for each of the plurality of blind voltages.Type: ApplicationFiled: January 13, 2022Publication date: February 16, 2023Applicant: SK hynix Inc.Inventors: June Young CHOI, Un Sang LEE
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Publication number: 20220262442Abstract: Disclosed is an operating method of a controller for controlling an operation of a semiconductor memory device including a plurality of memory cells. In the operating method of the controller, program data to be stored in a selected page of the semiconductor memory device is generated, and the semiconductor memory device is controlled to program the program data in the selected page. Bit data at a predetermined position in the program data is data for allowing a threshold voltage of a corresponding memory cell to maintain an erase state.Type: ApplicationFiled: August 5, 2021Publication date: August 18, 2022Applicant: SK hynix Inc.Inventors: Un Sang Lee, Moon Sik Seo
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Publication number: 20220189557Abstract: A memory device comprises a plurality of memory cells each having a threshold voltage corresponding to any one of a plurality of program states according to target data to be stored by performing a program operation, page buffers configured to store data provided from a memory controller, a data conversion controller configured to control the page buffers to convert the data into the target data including a plurality of logical page bits and a program operation controller configured to perform the program operation to store the target data in the plurality of memory cells, wherein the plurality of logical page bits include at least one logical page bit distinguishing even program states from odd program states among the plurality of program states and remaining logical page bits other than the at least one logical page bit having a same value as at least one program state among adjacent program states.Type: ApplicationFiled: March 7, 2022Publication date: June 16, 2022Inventors: Jong Woo KIM, Chi Wook AN, Un Sang LEE
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Patent number: 11328761Abstract: The memory device includes a memory block, a voltage generator, a pass switch group connecting or blocking the global lines and the local lines to each other or from each other in response to a block selection voltage, a decoder, and a logic circuit configured to control the decoder and the voltage generator so that the local lines are floated after initializing a channel of the strings and a voltage of the global lines is lower than a voltage of the global lines when initializing the channel of the strings, when a program operation of selected memory cells included in a selected page of the memory block is completed, the channels of the strings are initialized and the local lines are floated.Type: GrantFiled: October 21, 2020Date of Patent: May 10, 2022Assignee: SK hynix Inc.Inventors: Chi Wook An, Kyung Sub Park, Un Sang Lee
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Patent number: 11289165Abstract: A memory device may include: memory cells each having any one of first and second programmed states as a target programmed state; a peripheral circuit configured to perform a program operation so that each memory cell has a threshold voltage corresponding to the target programmed state; and a control circuit configured to control the peripheral circuit. The control circuit may include a program operation controller configured to control the peripheral circuit so that, during the program operation, an intermediate program operation is performed on the memory cells using an intermediate verify voltage, an additional program operation is performed on memory cells each having the second programmed state as a target programmed state if an intermediate verify operation passes, and a final program operation is performed on the memory cells such that each memory cell has a threshold voltage corresponding to the target programmed state.Type: GrantFiled: February 2, 2021Date of Patent: March 29, 2022Assignee: SK hynix Inc.Inventors: Un Sang Lee, Chi Wook An
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Publication number: 20210398583Abstract: The memory device includes a memory block including, a voltage generator, a pass switch group connecting or blocking the global lines and the local lines to each other or from each other in response to a block selection voltage, a decoder, and a logic circuit configured to control the decoder and the voltage generator so that the local lines are floated after initializing a channel of the strings and a voltage of the global lines is lower than a voltage of the global lines when initializing the channel of the strings, when a program operation of selected memory cells included in a selected page of the memory block is completed, the channels of the strings are initialized and the local lines are floated.Type: ApplicationFiled: October 21, 2020Publication date: December 23, 2021Applicant: SK hynix Inc.Inventors: Chi Wook AN, Kyung Sub PARK, Un Sang LEE
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Patent number: 11195586Abstract: A memory device and a method of operating the memory device are provided. The memory device includes a memory cell array including memory cells that are programmed into a plurality of program states, a peripheral circuit configured to perform a read operation on the memory cell array, and control logic configured to control the peripheral circuit to perform the read operation and to control the peripheral circuit to perform a masking process on first memory cells having a threshold voltage level higher than a first read level and second memory cells having a threshold voltage level lower than a second read level among the memory cells during the read operation.Type: GrantFiled: May 22, 2020Date of Patent: December 7, 2021Assignee: SK hynix Inc.Inventors: Jong Woo Kim, Chi Wook An, Un Sang Lee, Hwang Huh
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Patent number: 11061757Abstract: A memory device includes a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells; a program pulse information generator configured to generate program pulse information indicating whether a number of program pulses applied to the selected memory cells during the program operation has exceeded a reference value; and a status register configured to store status information and the program pulse information, wherein the memory device provides the status information and the program pulse information to an external controller in response to a command from the external controller.Type: GrantFiled: July 7, 2020Date of Patent: July 13, 2021Assignee: SK hynix Inc.Inventor: Un Sang Lee
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Publication number: 20210158875Abstract: A memory device may include: memory cells each having any one of first and second programmed states as a target programmed state; a peripheral circuit configured to perform a program operation so that each memory cell has a threshold voltage corresponding to the target programmed state; and a control circuit configured to control the peripheral circuit. The control circuit may include a program operation controller configured to control the peripheral circuit so that, during the program operation, an intermediate program operation is performed on the memory cells using an intermediate verify voltage, an additional program operation is performed on memory cells each having the second programmed state as a target programmed state if an intermediate verify operation passes, and a final program operation is performed on the memory cells such that each memory cell has a threshold voltage corresponding to the target programmed state.Type: ApplicationFiled: February 2, 2021Publication date: May 27, 2021Inventors: Un Sang LEE, Chi Wook AN
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Publication number: 20210118513Abstract: A memory device and a method of operating the memory device are provided. The memory device includes a memory cell array including memory cells that are programmed into a plurality of program states, a peripheral circuit configured to perform a read operation on the memory cell array, and control logic configured to control the peripheral circuit to perform the read operation and to control the peripheral circuit to perform a masking process on first memory cells having a threshold voltage level higher than a first read level and second memory cells having a threshold voltage level lower than a second read level among the memory cells during the read operation.Type: ApplicationFiled: May 22, 2020Publication date: April 22, 2021Applicant: SK hynix Inc.Inventors: Jong Woo KIM, Chi Wook AN, Un Sang LEE, Hwang HUH
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Patent number: 10937503Abstract: A memory device may include: memory cells each having any one of first and second programmed states as a target programmed state; a peripheral circuit configured to perform a program operation so that each memory cell has a threshold voltage corresponding to the target programmed state; and a control circuit configured to control the peripheral circuit. The control circuit may include a program operation controller configured to control the peripheral circuit so that, during the program operation, an intermediate program operation is performed on the memory cells using an intermediate verify voltage, an additional program operation is performed on memory cells each having the second programmed state as a target programmed state if an intermediate verify operation passes, and a final program operation is performed on the memory cells such that each memory cell has a threshold voltage corresponding to the target programmed state.Type: GrantFiled: October 16, 2019Date of Patent: March 2, 2021Assignee: SK hynix Inc.Inventors: Un Sang Lee, Chi Wook An
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Patent number: 10923201Abstract: Provided herein may be a memory device and a method of operating the memory device. The memory device may include: a memory block including a plurality of normal memory cells and a plurality of dummy memory cells; a peripheral circuit configured to perform an erase operation and a soft program operation on the memory block; and control logic configured to control the peripheral circuit to control the erase operation and the soft program operation, wherein during the soft program operation, threshold voltages of first dummy memory cells of the plurality of dummy memory cells are controlled to be higher than threshold voltages of second dummy memory cells of the plurality of dummy memory cells.Type: GrantFiled: October 3, 2019Date of Patent: February 16, 2021Assignee: SK hynix Inc.Inventor: Un Sang Lee
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Patent number: 10910047Abstract: A storage device includes a memory device configured to perform a read operation on a selected word line among a plurality of word lines, and a memory controller configured to control the memory device to: perform the read operation, perform a read retry operation on the selected word line, by changing a read voltage level, when the read operation fails, and perform an additional read retry operation on the selected word line, by changing the read voltage level and an application time of voltages related to the read operation, depending on whether the selected word line is a set word line, when the read retry operation fails.Type: GrantFiled: June 13, 2019Date of Patent: February 2, 2021Assignee: SK hynix Inc.Inventors: Un Sang Lee, Chi Wook An
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Patent number: 10878909Abstract: A semiconductor device includes: a memory string including a plurality of memory cells, a plurality of select transistors, and one or more dummy transistors coupled between the plurality of memory cells and the plurality of select transistors; one or more dummy word lines coupled to the one or more dummy transistors; and a plurality of select lines respectively coupled to the plurality of select transistors. When a program voltage is applied to a selected dummy word line among the one or more dummy word lines, a first dummy word line voltage may be applied to a select line adjacent to the one or more dummy word lines, among the plurality of select lines.Type: GrantFiled: July 15, 2019Date of Patent: December 29, 2020Assignee: SK hynix Inc.Inventor: Un Sang Lee
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Publication number: 20200395077Abstract: A memory device may include: memory cells each having any one of first and second programmed states as a target programmed state; a peripheral circuit configured to perform a program operation so that each memory cell has a threshold voltage corresponding to the target programmed state; and a control circuit configured to control the peripheral circuit. The control circuit may include a program operation controller configured to control the peripheral circuit so that, during the program operation, an intermediate program operation is performed on the memory cells using an intermediate verify voltage, an additional program operation is performed on memory cells each having the second programmed state as a target programmed state if an intermediate verify operation passes, and a final program operation is performed on the memory cells such that each memory cell has a threshold voltage corresponding to the target programmed state.Type: ApplicationFiled: October 16, 2019Publication date: December 17, 2020Inventors: Un Sang Lee, Chi Wook An
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Publication number: 20200334098Abstract: A memory device includes a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells; a program pulse information generator configured to generate program pulse information indicating whether a number of program pulses applied to the selected memory cells during the program operation has exceeded a reference value; and a status register configured to store status information and the program pulse information, wherein the memory device provides the status information and the program pulse information to an external controller in response to a command from the external controller.Type: ApplicationFiled: July 7, 2020Publication date: October 22, 2020Inventor: Un Sang LEE
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Publication number: 20200294606Abstract: Provided herein may be a memory device and a method of operating the memory device. The memory device may include: a memory block including a plurality of normal memory cells and a plurality of dummy memory cells; a peripheral circuit configured to perform an erase operation and a soft program operation on the memory block; and control logic configured to control the peripheral circuit to control the erase operation and the soft program operation, wherein during the soft program operation, threshold voltages of first dummy memory cells of the plurality of dummy memory cells are controlled to be higher than threshold voltages of second dummy memory cells of the plurality of dummy memory cells.Type: ApplicationFiled: October 3, 2019Publication date: September 17, 2020Applicant: SK hynix Inc.Inventor: Un Sang LEE
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Patent number: 10726932Abstract: A storage device includes a memory device configured to store program pulse information indicating whether the number of program pulses applied to selected memory cells during a program operation exceeds a reference value; and a memory controller configured to determine whether the probability of a growing defect occurring in the selected memory cells is present based on the program pulse information.Type: GrantFiled: October 8, 2018Date of Patent: July 28, 2020Assignee: SK hynix Inc.Inventor: Un Sang Lee