Abstract: A semiconductor device includes: a memory string including a plurality of memory cells, a plurality of select transistors, and one or more dummy transistors coupled between the plurality of memory cells and the plurality of select transistors; one or more dummy word lines coupled to the one or more dummy transistors; and a plurality of select lines respectively coupled to the plurality of select transistors. When a program voltage is applied to a selected dummy word line among the one or more dummy word lines, a first dummy word line voltage may be applied to a select line adjacent to the one or more dummy word lines, among the plurality of select lines.

Abstract: A storage device includes a memory device configured to perform a read operation on a selected word line among a plurality of word lines, and a memory controller configured to control the memory device to: perform the read operation, perform a read retry operation on the selected word line, changing a read voltage level, when the read operation fails, and perform an additional read retry operation on the selected word line, changing the read voltage level and an application time of voltages related to the read operation, depending on whether the selected word line is a set word line, when the read retry operation fails.

Abstract: A storage device includes a memory device configured to store program pulse information indicating whether the number of program pulses applied to selected memory cells during a program operation exceeds a reference value; and a memory controller configured to determine whether the probability of a growing defect occurring in the selected memory cells is present based on the program pulse information.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory cells each of which stores 2 or more bits of data. The peripheral circuit is configured to perform a program operation for the memory cells in the memory cell array. The control logic is configured to control the peripheral circuit and the memory cell array such that, during a program operation for target memory cells to be programmed among the memory cells, a preprogram for memory cells to be programmed to the highest program state is performed based on a predetermined value, and after the preprogram has been performed, a main program for the target memory cells to be programmed is performed.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory cells each of which stores 2 or more bits of data. The peripheral circuit is configured to perform a program operation for the memory cells in the memory cell array. The control logic is configured to control the peripheral circuit and the memory cell array such that, during a program operation for target memory cells to be programmed among the memory cells, a preprogram for memory cells to be programmed to the highest program state is performed based on a predetermined value, and after the preprogram has been performed, a main program for the target memory cells to be programmed is performed.

Abstract: The semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit unit configured to perform a program voltage applying operation, a first verifying operation, and a detrap voltage applying operation with respect to the plurality of memory cells, and a control logic unit configured to issue at least one command to the peripheral circuit unit to determine whether to perform the detrap voltage applying operation based on a result of the first verifying operation performed following the performance of the program voltage applying operation.

Abstract: The semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit unit configured to perform a program voltage applying operation, a first verifying operation, and a detrap voltage applying operation with respect to the plurality of memory cells, and a control logic unit configured to issue at least one command to the peripheral circuit unit to determine whether to perform the detrap voltage applying operation based on a result of the first verifying operation performed following the performance of the program voltage applying operation.