Patents by Inventor Uppili Sridhar

Uppili Sridhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12023667
    Abstract: A non-aqueous fluidic system for extracting, filtering and concentrating lipid biomarkers from geological samples includes a sample input for receiving a sample, a combined comminution-extraction unit, a filter in fluid communication with the container, and a concentrator operable to receive the solvent phase from the filter and to concentrate lipid extracts for further analysis. The combined comminution-extraction unit has a container into which the received sample is introduced, a port through which one or more organic solvents are introduced into the container for mixing with the sample to thereby extract lipids into an organic phase, and a comminutor configured to rotate in the container to pulverize the sample to a uniform, reduced particle size and comprising a sonicator configured to agitate and disperse the sample into the one or more organic solvents.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: July 2, 2024
    Assignee: United States of America as Represented by the Administrator of NASA
    Inventors: Mary Beth Wilhelm, Antonio Joseph Ricco, Morgan James Anderson, Linda Louise Jahnke, Kanchana Uppili Sridhar, Denise Kathleen Buckner, Padraig Michael Furlong
  • Patent number: 10475559
    Abstract: A process for producing a magnetic core material is disclosed. The process includes distributing particles within a solution medium to form a colloidal solution. The process further includes modifying a surface chemistry of the particles by adding one or more additives to the colloidal solution. The process further includes gelating the colloidal solution to form the magnetic core material.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: November 12, 2019
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Nazanin Davani, Joseph P. Ellul, Uppili Sridhar
  • Patent number: 9331048
    Abstract: A method including: providing a first wafer stack; applying a first bonding layer on the first wafer stack; providing a second wafer stack, where the second wafer stack includes vias; and applying a second bonding layer to the second wafer stack. The vias extend through the second wafer stack and to the second bonding layer. The second bonding layer is bonded to the first bonding layer. A seed layer is applied on a side of the second wafer stack opposite the second bonding layer such that a material of the seed layer (i) contacts the vias, and (ii) extends over and past ends of the second wafer stack and onto the first bonding layer.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: May 3, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Quanbo Zou, Uppili Sridhar, Amit S. Kelkar, Xuejun Ying
  • Patent number: 9184113
    Abstract: Methods of forming coaxial feedthroughs for 3d integrated circuits that provide excellent isolation of signal paths from the substrate and from adjacent feedthroughs. One method is to form a recess in a substrate and deposit alternate layers of insulation and conductive layers and then thin the substrate to make the layers available from both sides of the substrate, with the first metal layer forming the coaxial conductor and the second metal layer forming the central conductor. Alternatively the coaxial feedthroughs may be formed using a modified pillar process to form the coaxial conductor at the same time as the center conductor is formed so that the coaxial feedthrough is formed without requiring extra steps. Both processes are low temperature processes.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: November 10, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Uppili Sridhar, Albert Bergemont
  • Publication number: 20150132891
    Abstract: A method including: providing a first wafer stack; applying a first bonding layer on the first wafer stack; providing a second wafer stack, where the second wafer stack includes vias; and applying a second bonding layer to the second wafer stack. The vias extend through the second wafer stack and to the second bonding layer. The second bonding layer is bonded to the first bonding layer. A seed layer is applied on a side of the second wafer stack opposite the second bonding layer such that a material of the seed layer (i) contacts the vias, and (ii) extends over and past ends of the second wafer stack and onto the first bonding layer.
    Type: Application
    Filed: January 26, 2015
    Publication date: May 14, 2015
    Inventors: Quanbo Zou, Uppili Sridhar, Amit S. Kelkar, Xuejun Ying
  • Patent number: 9023422
    Abstract: A method of deposition of magnetic nanocomposites. The method comprises providing an electron beam evaporation system having at least two independent hearths with independently controllable electron beams, each to melt and evaporate materials in the respective hearth, each hearth having a respective shutter for selectively controlling the deposition of the respective material in the respective hearth, placing a ferromagnetic material in a first hearth, placing an oxide in a second hearth which, when evaporated and deposited, will form an insulator, maintaining an oxygen environment in the electron beam evaporation system while evaporating the materials in the first hearth and second hearth, and depositing the magnetic nanocomposite on at least one wafer in the electron beam evaporation system. Various aspects of the method are disclosed.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: May 5, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Uppili Sridhar, Joseph Paul Ellul
  • Patent number: 8970043
    Abstract: A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: March 3, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Quanbo Zou, Uppili Sridhar, Amit S. Kelkar, Xuejun Ying
  • Patent number: 8952768
    Abstract: A bulk acoustic wave (BAW) resonator is constructed to reduce phase and amplitude ripples in a frequency response. The BAW resonator is fabricated on a substrate 400 ?m thick or less, preferably approximately 325 ?m, having a first side and a polished second side with a peak-to-peak roughness of approximately 1000 A. A Bragg mirror having alternate layers of a high acoustic impedance material, such as tungsten, and a low acoustic impedance material is fabricated on the first side of the substrate. A BAW resonator is fabricated on the Bragg mirror. A lossy material, such as epoxy, coats the second side of the substrate opposite the first side. The lossy material has an acoustic impedance in the range of 0.01× to 1.0× the acoustic impedance of the layers of high acoustic impedance material.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: February 10, 2015
    Assignee: Triquint Semiconductor, Inc.
    Inventors: Edward Martin Godshalk, Rick D. Lutz, Masud Hannan, Ralph N. Wall, Uppili Sridhar
  • Patent number: 8940631
    Abstract: Methods of forming coaxial feedthroughs for 3d integrated circuits that provide excellent isolation of signal paths from the substrate and from adjacent feedthroughs. One method is to form a recess in a substrate and deposit alternate layers of insulation and conductive layers and then thin the substrate to make the layers available from both sides of the substrate, with the first metal layer forming the coaxial conductor and the second metal layer forming the central conductor. Alternatively the coaxial feedthroughs may be formed using a modified pillar process to form the coaxial conductor at the same time as the center conductor is formed so that the coaxial feedthrough is formed without requiring extra steps. Both processes are low temperature processes.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 27, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Uppili Sridhar, Albert Bergemont
  • Publication number: 20140347157
    Abstract: Exemplary embodiments provide a nanomagnetic structure and method of making the same, comprising a device substrate, a plurality of nanomagnetic composite layers disposed on the device substrate, wherein an adhesive layer is interposed between each of the plurality of nanomagnetic composite layers. Metal windings are integrated within the plurality of nanomagnetic composite layers to form an inductor core, wherein the nanomagnetic structure has a thickness ranging from about 5 to about 100 microns.
    Type: Application
    Filed: August 16, 2012
    Publication date: November 27, 2014
    Inventors: Markondeya Raj Pulugurtha, Rao R. Tummala, Venkatesh Sundaram, Nitesh Kumbhat, Uppili Sridhar, Joseph Ellul, Dibyajat Mishra
  • Patent number: 8686543
    Abstract: A 3D chip package is disclosed that includes a carrier substrate with a first cavity and a second cavity formed therein. A first structure is attached to the carrier substrate at least partially in the first cavity, and a second structure is attached to the carrier substrate at least partially in the second cavity, where the first and second structures include electrical circuitry. A shield layer may be disposed between the carrier substrate and the first structure and/or the second structure for isolating the first structure and/or the second structure at least one of electrically, magnetically, optically, or thermally. In some embodiments, the shield layer may be a dielectric shield layer for dielectrically coupling the first structure and the second structure. The first structure and the second structure may be homogeneous or heterogeneous.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: April 1, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Albert Bergemont, Uppili Sridhar, Joseph Ellul, Yi-Sheng Anthony Sun, Elliott Simons
  • Publication number: 20130335169
    Abstract: A bulk acoustic wave (BAW) resonator is constructed to reduce phase and amplitude ripples in a frequency response. The BAW resonator is fabricated on a substrate 400 ?m thick or less, preferably approximately 325 ?m, having a first side and a polished second side with a peak-to-peak roughness of approximately 1000 A. A Bragg mirror having alternate layers of a high acoustic impedance material, such as tungsten, and a low acoustic impedance material is fabricated on the first side of the substrate. A BAW resonator is fabricated on the Bragg mirror. A lossy material, such as epoxy, coats the second side of the substrate opposite the first side. The lossy material has an acoustic impedance in the range of 0.01× to 1.0× the acoustic impedance of the layers of high acoustic impedance material.
    Type: Application
    Filed: August 20, 2013
    Publication date: December 19, 2013
    Applicant: TriQuint Semiconductor, Inc.
    Inventors: Edward Martin Godshalk, Rick D. Lutz, Masud Hannan, Ralph N. Wall, Uppili Sridhar
  • Patent number: 8512800
    Abstract: Methods of reducing phase and amplitude ripples in a BAW resonator frequency response by providing a substrate, fabricating a Bragg mirror having alternate layers of a high acoustic material and a low acoustic material on a first surface of the substrate, fabricating a BAW on the Bragg mirror, and coating a second side of the substrate opposite the first side with a lossy material having an acoustic impedance in the range of 0.01× to 1.0× the acoustic impedance of the layers of high impedance material, the second surface of the substrate being a polished surface. Various embodiments are disclosed.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: August 20, 2013
    Assignee: Triquint Semiconductor, Inc.
    Inventors: Edward Martin Godshalk, Rick D. Lutz, Masud Hannan, Ralph N. Wall, Uppili Sridhar
  • Publication number: 20130105950
    Abstract: A 3D chip package is disclosed that includes a carrier substrate with a first cavity and a second cavity formed therein. A first structure is attached to the carrier substrate at least partially in the first cavity, and a second structure is attached to the carrier substrate at least partially in the second cavity, where the first and second structures include electrical circuitry. A shield layer may be disposed between the carrier substrate and the first structure and/or the second structure for isolating the first structure and/or the second structure at least one of electrically, magnetically, optically, or thermally. In some embodiments, the shield layer may be a dielectric shield layer for dielectrically coupling the first structure and the second structure. The first structure and the second structure may be homogeneous or heterogeneous.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 2, 2013
    Applicant: Maxim Integrated Products, Inc.
    Inventors: Albert Bergemont, Uppili Sridhar, Joseph Ellul, Yi-Sheng Anthony Sun, Elliott Simons
  • Publication number: 20120194306
    Abstract: A micro relay of a micro-electro-mechanical system (MEMS), includes a cap substrate, a first electrical contact, an actuator, and a second electrical contact. The first electrical contact is formed on the cap substrate, includes a platinum group metal, and includes a first surface layer of an oxide of the platinum group metal. The second electrical contact is formed on the actuator, includes the platinum group metal, and includes a second surface layer of the oxide of the platinum group metal. At least a first portion of the first surface layer contacts at least a second portion of the second surface layer during cycling of the micro relay.
    Type: Application
    Filed: February 1, 2011
    Publication date: August 2, 2012
    Applicant: Maxim Integrated Products, Inc.
    Inventors: Uppili Sridhar, Quanbo Zou, Amit S. Kelkar, Xuejun Ying
  • Publication number: 20120193808
    Abstract: A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.
    Type: Application
    Filed: February 1, 2011
    Publication date: August 2, 2012
    Applicant: Maxim Integrated Products, Inc.
    Inventors: Quanbo Zou, Uppili Sridhar, Amit S. Kelkar, Xuejun Ying
  • Patent number: 7863699
    Abstract: Bonded wafer packages having first and second wafers bonded together forming a matrix of sealed devices, at least one of the wafers having a plurality of passive devices formed thereon, including at least one BAW resonator within each of the sealed devices, the first wafer having conductor filled through-holes forming electrical connections between the passive devices and connections assessable from outside the sealed devices, the bonded wafers being diced to form individual sealed devices. The devices may be duplexers, interstage filters or other circuits such as VCOs and RF circuits. Various embodiments are disclosed.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: January 4, 2011
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Hans Dropmann, Uppili Sridhar, Carlton Stuebing
  • Publication number: 20090289722
    Abstract: Bonded wafer packages having first and second wafers bonded together forming a matrix of sealed devices, at least one of the wafers having a plurality of passive devices formed thereon, including at least one BAW resonator within each of the sealed devices, the first wafer having conductor filled through-holes forming electrical connections between the passive devices and connections assessable from outside the sealed devices, the bonded wafers being diced to form individual sealed devices. The devices may be duplexers, interstage filters or other circuits such as VCOs and RF circuits. Various embodiments are disclosed.
    Type: Application
    Filed: May 21, 2008
    Publication date: November 26, 2009
    Applicant: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Hans Dropmann, Uppili Sridhar, Carlton Stuebing
  • Publication number: 20090142480
    Abstract: Methods of reducing phase and amplitude ripples in a BAW resonator frequency response by providing a substrate, fabricating a Bragg mirror having alternate layers of a high acoustic material and a low acoustic material on a first surface of the substrate, fabricating a BAW on the Bragg mirror, and coating a second side of the substrate opposite the first side with a lossy material having an acoustic impedance in the range of 0.01x to 1.0x the acoustic impedance of the layers of high impedance material, the second surface of the substrate being a polished surface. Various embodiments are disclosed.
    Type: Application
    Filed: December 4, 2007
    Publication date: June 4, 2009
    Applicant: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Edward Martin Godshalk, Rick D. Lutz, Masud Hannan, Ralph N. Wall, Uppili Sridhar
  • Patent number: 7463125
    Abstract: Microrelays and microrelay fabrication and operating methods providing a microrelay actuator positively controllable between a switch closed position and a switch open position. The microrelays are a five terminal device, two terminals forming the switch contacts, one terminal controlling the actuating voltage on an actuator conductive area, one terminal controlling the actuating voltage on a first fixed conductive area, and one terminal controlling the actuating voltage on a second fixed conductive area deflecting the actuator in an opposite direction than the first fixed conductive area. Providing the actuating voltages as zero average voltage square waves and their complement provides maximum actuating forces, and positive retention of the actuator in both actuator positions. Various fabrication techniques are disclosed.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: December 9, 2008
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Uppili Sridhar, Quanbo Zou