Patents by Inventor Uwe Griebenow

Uwe Griebenow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9490189
    Abstract: A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: November 8, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer
  • Patent number: 9184095
    Abstract: In sophisticated semiconductor devices, the contact structure may be formed on the basis of contact bars formed in a lower portion of an interlayer dielectric material, which may then be contacted by contact elements having reduced lateral dimensions so as to preserve a desired low overall fringing capacitance. The concept of contact bars of reduced height level may be efficiently combined with sophisticated replacement gate approaches.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Sven Beyer, Uwe Griebenow, Jan Hoentschel, Andy Wei
  • Patent number: 9054207
    Abstract: Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: June 9, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Sven Beyer, Uwe Griebenow, Jan Hoentschel
  • Patent number: 8883582
    Abstract: During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: November 11, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Uwe Griebenow, Katrin Reiche, Heike Berthold
  • Publication number: 20140238045
    Abstract: A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase.
    Type: Application
    Filed: May 6, 2014
    Publication date: August 28, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer
  • Patent number: 8786027
    Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: July 22, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer
  • Patent number: 8759960
    Abstract: In a stacked semiconductor device, a Peltier element may be incorporated as a distributed element so as to provide active heat transfer from a high power device into a low power device, thereby achieving superior temperature control in stacked device configurations. For example, a CPU and a dynamic RAM device may be provided as a stacked configuration, wherein waste heat of the CPU may be efficiently distributed into the low power memory device.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: June 24, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer
  • Patent number: 8748281
    Abstract: When forming sophisticated high-k metal gate electrode structures, the removal of a dielectric cap material may be accomplished with superior process uniformity by using a silicon dioxide material. In other illustrative embodiments, an enhanced spacer regime may be applied, thereby also providing superior implantation conditions for forming drain and source extension regions and drain and source regions.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: June 10, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Sven Beyer, Thilo Scheiper, Uwe Griebenow
  • Patent number: 8735237
    Abstract: The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: May 27, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Kai Frohberg, Frank Feustel, Thomas Werner
  • Patent number: 8673713
    Abstract: A non-conformal metal silicide in a transistor of recessed drain and source configuration may provide enhanced efficiency with respect to strain-inducing mechanisms, drain/source resistance and the like. For this purpose, in some cases, an amorphizing implantation process may be performed prior to the silicidation process, while in other cases an anisotropic deposition of the refractory metal may be used.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: March 18, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jan Hoentschel, Uwe Griebenow, Andy Wei
  • Patent number: 8669151
    Abstract: Sophisticated high-k metal gate electrode structures are provided on the basis of a hybrid process strategy in which the work function of certain gate electrode structures is adjusted in an early manufacturing stage, while, in other gate electrode structures, the initial gate stack is used as a dummy material and is replaced in a very advanced manufacturing stage. In this manner, superior overall process robustness in combination with enhanced device performance may be achieved.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: March 11, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Sven Beyer, Thilo Scheiper, Uwe Griebenow
  • Patent number: 8615145
    Abstract: In an integrated circuit device, such as a microprocessor, a device internal optical communication system is provided in order to enhance signal transfer capabilities while relaxing overall thermal conditions. Furthermore, the device internal optical data or signal transfer capabilities may result in superior operating speed and a high degree of design flexibility. The optical communication system may be applied as a chip internal system in single chip systems or as an inter-chip optical system in three-dimensional chip configurations provided in a single package.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: December 24, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Kai Frohberg, Jan Hoentschel
  • Publication number: 20130299891
    Abstract: Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.
    Type: Application
    Filed: July 9, 2013
    Publication date: November 14, 2013
    Inventors: Thilo Scheiper, Sven Beyer, Uwe Griebenow, Jan Hoentschel
  • Patent number: 8574991
    Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: November 5, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Uwe Griebenow, Maciej Wiatr
  • Publication number: 20130252409
    Abstract: During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability.
    Type: Application
    Filed: May 20, 2013
    Publication date: September 26, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Uwe Griebenow, Katrin Reiche, Heike Berthold
  • Patent number: 8541885
    Abstract: By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: September 24, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Martin Gerhardt, Ralf Richter, Thomas Feudel, Uwe Griebenow
  • Publication number: 20130240988
    Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.
    Type: Application
    Filed: May 3, 2013
    Publication date: September 19, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer
  • Patent number: 8536036
    Abstract: In a process strategy for forming high-k metal gate electrode structures in an early manufacturing phase, a predoped semiconductor material may be used in order to reduce the Schottky barrier between the semiconductor material and the conductive cap material of the gate electrode structures. Due to the substantially uniform material characteristics of the predoped semiconductor material, any patterning-related non-uniformities during the complex patterning process of the gate electrode structures may be reduced. The predoped semiconductor material may be used for gate electrode structures of complementary transistors.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: September 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Jan Hoentschel, Uwe Griebenow, Thilo Scheiper
  • Patent number: 8507348
    Abstract: Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: August 13, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Sven Beyer, Uwe Griebenow, Jan Hoentschel
  • Patent number: 8508008
    Abstract: In a semiconductor device, optical signal transfer capabilities are implemented on the basis of silicon-based monolithic opto-electronic components in combination with an appropriate waveguide. Thus, in complex circuitries, such as microprocessors and the like, superior performance may be obtained in terms of signal propagation delay, while at the same time thermal requirements may be less critical.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: August 13, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Sven Beyer, Thilo Sheiper, Jan Hoentschel