Abstract: An apparatus and method for reducing the time required to supply a processor core with instructions uses a cache memory, a cache controller, and an instruction predecoding unit. When a line of instructions is retrieved into the cache memory, the instruction predecoding unit inspects the instructions in the line to determine if the line contains any nonsequential instructions. The cache controller stores an indication of whether the line contains nonsequential instructions with the line of instructions in the cache memory. If a given line of instructions does not contain any nonsequential instructions, the line of instructions following the given line is retrieved into the cache memory when one of the instructions in the given line is requested by the processor core.

Abstract: A method and device for avoiding unnecessary data broadcasts by detecting the presence of additional cache-equipped bus-masters is provided. The device includes a master bus-master equipped with a local cache arrangement for caching data originating in a system memory. The master bus-master communicates with the system memory over a bus, and is coupled to a control line at an input. Any cache-equipped slave bus masters that are caching data with the system memory are coupled to the control line by an output and are configured to generate a signal at the output to drive the control line to a predetermined state to indicate that they are caching data. The master bus-master detects the state of the control line and determines whether the data being buffered in its local cache arrangement is shared based upon the state of the control line.

Abstract: A method and mechanism for controlling the data transfers between a system memory and a cache memory is provided. The mechanism includes a cache controller with a physical address register coupled to a bus. Software may alter the operation of the cache controller to force blocks in the cache memory to be written back to the system memory by sending control signals to the physical address register over the bus.