Abstract: The invention relates to a MOS memory unit for serial information processing, in particular a shift register stage with an EEPROM cell having a floating gate transistor. According to the prior art, the gate electrodes of all floating gate transistors of a memory unit have the same potential. The result is that two programming cycles must be performed for complete programming, entailing a high current consumption. In accordance with the invention, the drain electrode of the floating gate transistor is connected via an inverter stage to its gate electrode. This halves the total programming time and hence also the total programming current in comparison with the prior art.