Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a failure analysis module comprising a program of instructions, the failure analysis module configured to, when read and executed by the processor, set a predictive failure threshold for each of the plurality of non-volatile memories based at least on functional parameters of such non-volatile memory, and adapt the predictive failure threshold for each of the plurality of non-volatile memories based at least on health status parameters of such non-volatile memory.

Abstract: An information handling system includes interleaved dual in-line memory modules (DIMMs) that are partitioned into logical partitions, wherein each logical partition is associated with a namespace. A DIMM controller sets a custom DIMM-level namespace-based threshold to detect a DIMM error and to identify one of the logical partitions of the DIMM error using the namespace associated with the logical partition. The detected DIMM error is repaired if it exceeds an error correcting code (ECC) threshold.

Abstract: A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.

Abstract: A dual-channel Dual In-Line Memory Module (DIMM) includes a first memory element configured to perform memory transactions for first memory locations associated with the first memory element via a first memory channel of the dual-channel DIMM, and a second memory element configured to perform memory transactions for second memory locations associated with the second memory element via a second memory channel of the dual-channel DIMM, wherein the first memory channel is different than the second memory channel, and wherein the first memory element is a different type of memory element than the second memory element.

Abstract: A dual in-line memory module (DIMM) thermal control system for intelligent DIMM thermal controls for maximum uptime may include a memory subsystem. The memory subsystem may include a first DIMM and a first serial presence detect (SPD) module associated with the first DIMM. The DIMM thermal control system may also include a baseboard management controller (BMC). The BMC may, when a first DIMM failure of the first DIMM may be detected, record a first failure event in a first failure events log of the first SPD module. The first failure event may comprise the first DIMM failure and associated first thermal telemetry data of the first DIMM. The BMC may also adjust DIMM thermal control settings to reduce temperature of the first DIMM based on the first failure events log including at least the first failure event.

Abstract: An information handling system includes interleaved dual in-line memory modules (DIMMs) that are partitioned into logical partitions, wherein each logical partition is associated with a namespace. A DIMM controller sets a custom DIMM-level namespace-based threshold to detect a DIMM error and to identify one of the logical partitions of the DIMM error using the namespace associated with the logical partition. The detected DIMM error is repaired if it exceeds an error correcting code (ECC) threshold.

Abstract: An information handling system includes interleaved dual in-line memory modules (DIMMs) that are partitioned into logical partitions, wherein each logical partition is associated with a namespace. A DIMM controller sets a custom DIMM-level namespace-based threshold to detect a DIMM error and to identify one of the logical partitions of the DIMM error using the namespace associated with the logical partition. The detected DIMM error is repaired if it exceeds an error correcting code (ECC) threshold.

Abstract: An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor to receive the interrupts, accumulate a count of the interrupts, and provide a first error indication when the count exceeds a first error threshold. The failure predictor increments the count each time the predictor receives a particular interrupt and decrements the count in accordance with an error leak rate. The error leak rate has a first value when the DIMM is newer than a first age threshold and has a second value when the DIMM is older than the first age threshold.

Abstract: A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a memory system communicatively coupled to the processor. The memory system may include one or more persistent memory modules, each of the one or more persistent memory modules comprising a volatile memory and a non-volatile memory and one or more health registers accessible to a host system executing on the processor, the health registers storing health information indicating, for each of a plurality of ranks of the volatile memory, whether the memory system can reliably perform a save operation to a portion of non-volatile memory mapped to volatile memory of the rank.

Abstract: An information handling system for DIMM provisioning and RAS enablement may include a memory subsystem that may comprise a DIMM including a set of ranks, each rank of the set of ranks may include a set of DRAMs, each DRAM of the set of DRAMs including a set of rows, and a non-volatile memory associated with the DIMM. The DIMM may include a post package repair (PPR) history including a set of PPR history entries. Each PPR history entry of the set of PPR history entries may include a failed row count for each rank of a corresponding DRAM of the DIMM. The information handling system may also include a BIOS that may determine whether health of the DIMM is unhealthy that may be based on the PPR history. When the health of the DIMM may be unhealthy, the BIOS may also perform a PPR corrective action procedure.

Abstract: An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor that receives the interrupts, accumulates a count of the interrupts, and provides an error indication when the count exceeds an error threshold. The failure predictor receives a first in time interrupt, suspends the accumulation of the count for a first duration of time in response to receiving the first in time interrupt, and resumes the accumulation of the count. In resuming the accumulation of the count, the failure predictor increments the count each time the predictor receives a first subsequent interrupt and decrements the count in accordance with an error leak rate.

Abstract: A memory subsystem includes one or more communication channels that enable communication with more than one memory module of an information handling system (IHS). A memory controller of the memory subsystem is in communication with the one or more communication channels. In response to determining that one or more lines fail signal integrity testing at a target communication speed, the memory controller invokes an error checking and correcting (ECC) mode that reassigns lines of the communication channel for carrying data and ECC code. Lines that passed signal integrity testing are assigned to carrying data and ECC code. Lines that failed signal integrity testing are not used.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a persistent memory system communicatively coupled to the processor, the persistent memory system comprising one or more persistent memory modules and a plurality of targeted save registers, each targeted save register associated with a respective portion of the persistent memory system, and each targeted save register having a value indicative of how save operations from volatile memory to non-volatile memory of the persistent memory system are to be performed with respect to the respective portion of the persistent memory system.

Abstract: A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.

Abstract: In one or more embodiments, one or more methods, processes, and/or systems may receive quality of service (QoS) configuration information associated with information storage and retrieval of a device coupled to an input/output memory management unit (IOMMU); may configure one or more registers of the memory controller with a range of addresses associated; may determine performance data based at least on one or more of an average number of transactions completed, an average number of cycles utilized by the transactions, and an average number of credits in a flow control between the memory controller and a first memory medium coupled to the memory controller; may determine that the performance data does not comply with the QoS configuration information; and if the performance data indicates that the information storage and retrieval of the device is congested, may remap the IOMMU to point to DMA buffers of a second memory medium.

Abstract: An information handling system for DIMM provisioning and RAS enablement may include a memory subsystem that may comprise a DIMM including a set of ranks, each rank of the set of ranks may include a set of DRAMs, each DRAM of the set of DRAMs including a set of rows, and a non-volatile memory associated with the DIMM. The DIMM may include a post package repair (PPR) history including a set of PPR history entries. Each PPR history entry of the set of PPR history entries may include a failed row count for each rank of a corresponding DRAM of the DIMM. The information handling system may also include a BIOS that may determine whether health of the DIMM is unhealthy that may be based on the PPR history. When the health of the DIMM may be unhealthy, the BIOS may also perform a PPR corrective action procedure.

Abstract: An information handling system includes interleaved dual in-line memory modules (DIMMs) that are partitioned into logical partitions, wherein each logical partition is associated with a namespace. A DIMM controller sets a custom DIMM-level namespace-based threshold to detect a DIMM error and to identify one of the logical partitions of the DIMM error using the namespace associated with the logical partition. The detected DIMM error is repaired if it exceeds an error correcting code (ECC) threshold.

Abstract: In one or more embodiments, one or more methods, processes, and/or systems may receive quality of service (QoS) configuration information associated with information storage and retrieval of a device coupled to an input/output memory management unit (IOMMU); may configure one or more registers of the memory controller with a range of addresses associated; may determine performance data based at least on one or more of an average number of transactions completed, an average number of cycles utilized by the transactions, and an average number of credits in a flow control between the memory controller and a first memory medium coupled to the memory controller; may determine that the performance data does not comply with the QoS configuration information; and if the performance data indicates that the information storage and retrieval of the device is congested, may remap the IOMMU to point to DMA buffers of a second memory medium.

Abstract: An information handling system includes a plurality of storage class memory (SCM) devices and a processor. Each SCM device is configured to determine a health indication of the SCM device. The processor is configured to execute code to provide a basic input/output system (BIOS). The BIOS receives the health indications, ranks the SCMs based upon the health indications, determines that a first BIOS function has a first quality of service level, and allocates the first BIOS function to a first SCM based upon the first quality of service level, wherein the first SCM has a highest rank of the SCMs.