Abstract: A dynamic random access memory (DRAM) device includes a plurality of bank groups of first storage cells, each bank group arranged as a plurality of banks, each bank arranged as a plurality of rows, and each row including a plurality of dynamic storage cells. The DRAM device further includes a post-package repair (PPR) storage array arranged as a plurality of entries, wherein the DRAM device is configured to map a first row failure in a first bank group to a first entry of the PPR storage array, and to map a second row failure in a second bank group to a second entry of the PPR storage array.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a memory system communicatively coupled to the processor. The memory system may include one or more persistent memory modules, each of the one or more persistent memory modules comprising a volatile memory and a non-volatile memory and one or more health registers accessible to a host system executing on the processor, the health registers storing health information indicating, for each of a plurality of ranks of the volatile memory, whether the memory system can reliably perform a save operation to a portion of non-volatile memory mapped to volatile memory of the rank.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a persistent memory system communicatively coupled to the processor, the persistent memory system comprising one or more persistent memory modules and a plurality of targeted save registers, each targeted save register associated with a respective portion of the persistent memory system, and each targeted save register having a value indicative of how save operations from volatile memory to non-volatile memory of the persistent memory system are to be performed with respect to the respective portion of the persistent memory system.

Abstract: An information handling system includes a receiver and a transmitter. A margin detector of the receiver derives an eye plot for signals received via a plurality of high speed serial lanes. A first control module of the receiver identifies a weakest lane of the high speed serial lanes, and compares eye plots for a signal on the weakest lane from one crosstalk minimization iteration to the next. A second control module of the transmitter receives a signal from the first control module indicating whether an eye plot of the signal has improved from one crosstalk minimization iteration to the next, and iteratively controls a phase shift of aggressor signals in the high speed serial lanes during each iteration until the eye plot of the signal remains the same from one iteration to the next. A phase shift module of the transmitter phase shifts the aggressor signals during each iteration.

Abstract: A DIMM includes first and second DRAM devices, each configured to perform memory transactions for memory locations associated with the DRAM device via a respective first and second memory channel. The DIMM also includes a non-volatile memory device and a DIMM controller. The DIMM controller stores data from the first and second memory locations to the non-volatile memory device in response to a save data operation, receives an indication that communication via the first memory channel has failed, stores the first data from the non-volatile memory device to the second DRAM device in response to the indication and a restore data operation, provides an indication that the data is stored on the second DRAM device, receives an indication that the data has been read, stores the second data from the non-volatile memory device to the second DRAM device, and provides an indication that the second data is stored on the second DRAM device.

Abstract: An information handling system includes a first memory module having a volatile memory, a non-volatile memory, and a save controller configured to execute a save operation that transfers at least all modified information of the volatile memory to the nonvolatile memory. A power-down controller of the information handling system is connected to the first memory module, and includes a first input to receive a first indicator that indicates the first memory module is to perform the save operation, a second input to receive a second indicator that indicates a thermal characteristic of the system, and control circuitry to provide the save operation indicator to the first memory module to initiate the save operation in response to receiving the first indicator.

Abstract: An information handling system includes a first memory module having a volatile memory, a non-volatile memory, and a save controller configured to execute a save operation that transfers at least all modified information of the volatile memory to the nonvolatile memory. A power-down controller of the information handling system is connected to the first memory module, and includes a first input to receive a first indicator that indicates the first memory module is to perform the save operation, a second input to receive a second indicator that indicates a thermal characteristic of the system, and control circuitry to provide the save operation indicator to the first memory module to initiate the save operation in response to receiving the first indicator.

Abstract: A memory device update system includes a computing device couple to a management device. While the computing device is in a pre-boot environment, a memory device update engine in the computing device assigns a memory type, which is associated with the storage of memory device update information, to memory region(s) in a memory subsystem in the computing device. Subsequent to a boot of the computing device such that the computing device is in a runtime environment, the memory device update engine retrieves memory device update information from the management device and uses a data communication interface between the memory device update engine and the memory subsystem to write the memory device update information to the memory region(s) that were assigned the memory type. While the computing device is in the runtime environment, the memory subsystem then uses the memory device update information to update the memory subsystem.

Abstract: A dual-channel Dual In-Line Memory Module (DIMM) includes a first memory element configured to perform memory transactions for first memory locations associated with the first memory element via a first memory channel of the dual-channel DIMM, and a second memory element configured to perform memory transactions for second memory locations associated with the second memory element via a second memory channel of the dual-channel DIMM, wherein the first memory channel is different than the second memory channel, and wherein the first memory element is a different type of memory element than the second memory element.

Abstract: A DIMM includes a DRAM device and a non-volatile memory device. The DIMM is configured to determine that first data stored on the DRAM device is modified data and that second data stored on the DRAM device is unmodified data, and perform a save data operation to transfer the data from the DRAM device to the non-volatile memory device, wherein the save data operation comprises transferring the first data and not transferring the second data.

Abstract: A DIMM includes a DRAM device and a non-volatile memory device. The DIMM is configured in a first mode to receive a save signal from a memory controller via a save pin of the DIMM and to perform a first save operation to transfer data from the DRAM device to the non-volatile memory device in response to receiving the save signal. The DIMM is further configured in a second mode to receive a save command from the memory controller via a command bus of the DIMM and to perform a second save operation to transfer the data from the DRAM device to the non-volatile memory device in response to receiving the save command.

Abstract: A DIMM includes first and second DRAM devices, each configured to perform memory transactions for memory locations associated with the DRAM device via a respective first and second memory channel. The DIMM also includes a non-volatile memory device and a DIMM controller. The DIMM controller stores data from the first and second memory locations to the non-volatile memory device in response to a save data operation, receives an indication that communication via the first memory channel has failed, stores the first data from the non-volatile memory device to the second DRAM device in response to the indication and a restore data operation, provides an indication that the data is stored on the second DRAM device, receives an indication that the data has been read, stores the second data from the non-volatile memory device to the second DRAM device, and provides an indication that the second data is stored on the second DRAM device.

Abstract: An information handling system includes a memory controller and a Dual In-Line Memory Module (DIMM) including a Dynamic Random Access Memory (DRAM) device. The DRAM device is configured to detect an Error Correcting Code (ECC) bit error for a data transaction within the DRAM device, determine if the ECC bit error results in an ECC error threshold being exceeded, and provide an alert signal to the memory controller in response to determining that the ECC bit error resulted in the ECC error threshold being exceeded.

Abstract: A dual-channel Dual In-Line Memory Module (DIMM) is configured to provide memory transactions on a first memory channel and a second memory channel. The dual-channel DIMM includes a first bank of Dynamic Random Access Memory (DRAM) devices configured to provide a first memory transaction on the first memory channel, a second bank of DRAM devices configured to provide a second memory transaction on the second memory channel, and a plurality of back door communication paths, each back door communication path being between a data bit of the first bank of DRAM devices and a corresponding data bit of the second bank of DRAM devices.

Abstract: A system includes a memory device and a memory controller. The memory device has a data pin and a first available pin. The memory controller has a data pin coupled to the data pin of the memory device, and has a first available pin coupled to the first available pin of the memory device. The memory controller transfers memory data on the first available pin of the memory controller, and the memory device receives memory data on the first available pin of the memory device.

Abstract: An information handling system includes a receiver and a transmitter. A margin detector of the receiver derives an eye plot for signals received via a plurality of high speed serial lanes. A first control module of the receiver identifies a weakest lane of the high speed serial lanes, and compares eye plots for a signal on the weakest lane from one crosstalk minimization iteration to the next. A second control module of the transmitter receives a signal from the first control module indicating whether an eye plot of the signal has improved from one crosstalk minimization iteration to the next, and iteratively controls a phase shift of aggressor signals in the high speed serial lanes during each iteration until the eye plot of the signal remains the same from one iteration to the next. A phase shift module of the transmitter phase shifts the aggressor signals during each iteration.

Abstract: An information handling system may implement a method for controlling cache flush size by limiting the amount of modified cached data in a data cache at any given time. The method may include keeping a count of the number of modified cache lines (or modified cache lines targeted to persistent memory) in the cache, determining that a threshold value for modified cache lines is exceeded and, in response, flushing some or all modified cache lines to persistent memory. The threshold value may represent a maximum number or percentage of modified cache lines. The cache controller may include a field for each cache line indicating whether it targets persistent memory. Limiting the amount of modified cached data at any given time may reduce the number of cache lines to be flushed in response to a power loss event to a number that can be flushed using the available hold-up energy.

Abstract: A memory controller for dual-channel DDR DIMMs comprises a first memory channel configured to execute a first memory transaction with a first memory device of a dual-channel DDR DIMM, and a second memory channel configured to execute a second memory transaction with a second memory device of the dual-channel DDR DIMM. The memory controller is configured to determine that the first memory channel is experiencing a degraded performance level in executing the first memory transaction with the first device, and to prevent read-write memory transactions and write-read memory transactions on the first and second memory channels in response to determining that the first memory channel is experiencing the degraded performance level.

Abstract: A memory channel includes a dual channel double data rate (DDR) memory device having a first bank of memory accessed by a first data bus and a first command/address (C/A) bus, and a second bank of memory accessed by a second data bus and a second C/A bus, and a memory controller configured to train the first and second C/A busses with both the first and second C/A busses active, and to train one of the first and second C/A busses with the other of the first and second C/A busses idle.

Abstract: A system includes a memory device and a memory controller. The memory device has a data pin and a first available pin. The memory controller has a data pin coupled to the data pin of the memory device, and has a first available pin coupled to the first available pin of the memory device. The memory controller transfers memory data on the first available pin of the memory controller, and the memory device receives memory data on the first available pin of the memory device.