Abstract: A radio frequency (RF) integrated circuit (IC) operable to support wireless communications is provided. In one embodiment, the RF IC includes an advanced high-performance (AHB) bus matrix, a microprocessor core coupled to the AHB bus matrix, a plurality of processing modules wherein each processing module is operable to support one or more functions of the RF IC, and a plurality of power islands. Each power island is associated with one or more functions of the RF IC. This arrangement allows power islands coupled to the processing modules associated with the one or more functions associated with the power island to supply power for the processing modules associated with the one or more functions associated with the power island. Power from the power island(s) to the processing module(s) may be reduced or secured when the one or more functions associated with the power island is not required.

Abstract: An integrated circuit (IC) includes an RF section, a DSP, and a plurality of processors. The RF section and the DSP process an inbound RF signal to produce inbound data and process outbound data to produce an outbound RF signal. In addition, the DSP converts an outbound analog audio signal into an outbound digital audio signal and converts an inbound digital audio signal into an inbound analog audio signal. A first processor converts the inbound data into the inbound digital audio signal and converts the outbound digital audio signal into the outbound data. A second processor performs a user application that includes at least one of generation of the inbound analog audio signal and generation of the outbound analog audio signal and performs an operating system algorithm to coordinate operation of the user application.

Abstract: An integrated circuit (IC) includes a first die, a second die, a packaging substrate, and coupling circuit. The first die includes first circuitry and the second die includes second circuitry. The packaging substrate supports the first and second dies, wherein the first and second dies are stacked with respect to the packaging substrate. The coupling circuit couples the first die to the second die, wherein the first and second circuitry communicate via the coupling circuit.

Abstract: A single chip wireless transceiver operable to perform voice, data and radio frequency (RF) processing is provided. This processing may be divided between various processing modules. This single chip includes a processing module having an ARM microprocessor and a digital signal processor (DSP), an RF section, and an interface module. The processing module converts an outbound voice signal into an outbound voice symbol stream, converts an inbound voice symbol stream into an inbound voice signal, converts outbound data into an outbound data symbol stream, and converts an inbound data symbol stream into inbound data. These functions may be divided between the ARM microprocessor and DSP, where the DSP supports physically layer type applications and the ARM microprocessor supports higher layer applications. Further bifurcation may be based on voice applications, data applications, and/or RF control.

Abstract: An RFIC includes an RF section, a memory interface, a display interface, an audio codec, a bus matrix, and a processing unit. The RF section converts a first inbound RF signal into a first inbound symbol stream and converts a second inbound RF signal into a second inbound symbol stream. The memory interface is operably coupled to retrieve a video file from memory and the display interface is operable to provide video data to a display. The audio codec converts an output digital signal into an output voice signal. The processing unit converts the first inbound symbol stream into streaming video data; converts the second inbound symbol stream into the output digital signal; and facilitates providing, via the bus matrix, at least one of: the video file to the display interface as the video data; the streaming video data to the display interface as the video data; and the digital output signal to the audio codec.

Abstract: A single chip wireless transceiver operable to perform voice, data and radio frequency (RF) processing is provided. This processing may be divided between various processing modules. This single chip includes a processing module having an ARM microprocessor and a digital signal processor (DSP), an RF section, and an interface module. The processing module converts an outbound voice signal into an outbound voice symbol stream, converts an inbound voice symbol stream into an inbound voice signal, converts outbound data into an outbound data symbol stream, and converts an inbound data symbol stream into inbound data. These functions may be divided between the ARM microprocessor and DSP, where the DSP supports physically layer type applications and the ARM microprocessor supports higher layer applications. Further bifurcation may be based on voice applications, data applications, and/or RF control.

Abstract: A communication device includes a voice data and RF integrated circuit (IC) that includes a memory module that stores a plurality of applications corresponding to a plurality of uses of the communication device. A processing module executes a selected one of the plurality of applications and selects one of a plurality of power modes based on a current one of the plurality of uses of the communication device corresponding to the selected one of the plurality of applications. The processing module generates a power mode signal based on the selected one of the plurality of power modes. An off-chip power management circuit receives the power mode signal and that generates a plurality of power supply signals to the voice data and RF IC based on the power mode signal.

Abstract: An RFIC includes first and second RF sections, first and second PHY processing modules, first and second upper layer processing modules, and memory. When the RFIC is in a first receive mode, the first RF section, the first PHY processing module, and the first upper layers processing module convert a first inbound RF signal into a first inbound audio signal in accordance with a first wireless communication protocol. When the RFIC is in a second receive mode, the second RF section, the second PHY processing module, and the second upper layers processing module convert a second inbound RF signal into a second inbound audio signal in accordance with a second wireless communication protocol. The memory stores the first and second inbound audio signals. The first PHY processing module retrieves, based on the receive mode, the first or second inbound audio signal from the memory and converts the first or second inbound audio signal into a first or second inbound analog audio signal.

Abstract: A real-time/non-real-time/RF IC includes first and second baseband processing modules, an RF section, a wireline interface, and a bus structure. The first baseband processing module converts real-time outbound data into real-time outbound symbols and converts real-time inbound symbols into real-time inbound data. The second baseband processing module converts non-real-time outbound data into non-real-time outbound symbols and converts non-real-time inbound symbols into non-real-time inbound data. The RF section converts the real-time outbound symbols into real-time outbound RF signals, converts real-time inbound RF signals into the real-time inbound symbols, converts the non-real-time outbound symbols into non-real-time outbound RF signals, and converts non-real-time inbound RF signals into the non-real-time symbols. The wireline interface couples the non-real-time outbound data, the non-real-time inbound data, the real-time outbound data, and/or the real-time inbound data to an off-chip wireline connection.

Abstract: An adjustable antenna interface includes a single-ended to differential conversion circuit, an adjustable impedance matching circuit, an RF differential switch, and an input. The single-ended to differential conversion circuit converts inbound RF signals from single-ended signals to differential signals and converts outbound RF signals from differential signals to single-ended signals. The adjustable impedance matching circuit provides an impedance based on an impedance control signal. The RF differential switch provides the differential outbound RF signals from the IC to the single-ended to differential conversion circuit in accordance with a first antenna control signal and provides the differential inbound RF signals from the single-ended to differential conversion circuit to the IC in accordance with a second antenna control signal. The input receives the first antenna control signal, the second antenna control signal, and the impedance control signal from the IC.

Abstract: A communication device includes a voice data and RF integrated circuit (IC) that includes a memory module that stores a least one application as a plurality of operational instructions, the at least one application having a plurality of power modes that each correspond to one of a plurality of use characteristics. A processing module executes the plurality of operational instructions and determines a selected one of the plurality of power modes based on current use characteristics of the at least one application, and the generates a power mode signal based on the selected one of the plurality of power modes. An off-chip power management circuit receives the power mode signal and that generates a plurality of power supply signals to the voice data and RF IC based on the power mode signal.

Abstract: A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.

Abstract: A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.

Abstract: An adjustable antenna interface includes a single-ended to differential conversion circuit, an adjustable impedance matching circuit, an RF differential switch, and an input. The single-ended to differential conversion circuit converts inbound RF signals from single-ended signals to differential signals and converts outbound RF signals from differential signals to single-ended signals. The adjustable impedance matching circuit provides an impedance based on an impedance control signal. The RF differential switch provides the differential outbound RF signals from the IC to the single-ended to differential conversion circuit in accordance with a first antenna control signal and provides the differential inbound RF signals from the single-ended to differential conversion circuit to the IC in accordance with a second antenna control signal. The input receives the first antenna control signal, the second antenna control signal, and the impedance control signal from the IC.

Abstract: A system and method for regulating power consumption within an integrated circuit (IC) with a modular design. The IC is designed so that any one distinct functional module within the IC utilizes only transistors with a substantially same or similar critical voltage level, which may for example be the threshold voltage of the transistors. Consequently, the supply voltage delivered to each functional modules can be lowered to the minimum voltage necessary to enable the transistors within the module to operate. Similarly, modules within the IC may be designed with transistors which share a common value for a substrate bias voltage or a clock speed, or with a combination of common values for several electrical factors. In this way, it is possible to reduce power consumption by fine-tuning the voltages supplied to (or clock speeds driving) specific modules, in a way which is custom-tuned to each module.

Abstract: A high-speed, low leakage-power Standard Cell Library is provided. The high-speed, low-leakage-power Standard Cell Library provides the extra drive-strength of a taller X-Track library (e.g., 14-Track library) and low leakage-power comparable to that of a smaller, N-Track library (e.g., 10-Track library). The high-speed, low leakage-power Standard Cell Library includes a set of cells each having a device area designed to provide maximum drive strength for the cell. The high-speed, low leakage-power Standard Cell Library further includes a second set of cells having varying device areas that provide reduced leakage power characteristics comparable to cells in the smaller, N-Track library. The modified reduced leakage-power cells are formed by adding padding to the cell to achieve a desired leakage-power characteristic of the cell.

Abstract: An on-chip baseband-to-RF interface includes a receive/transmit section, a control section, and a clock section. The receive/transmit section, when in a receive mode, provides the stream of inbound symbols from the RF circuit to the baseband processing module and, when in a transmit mode, provides the stream of outbound symbols from the baseband processing module to the RF circuit. The control section provides a control communication path between the baseband processing module and the RF circuit. The clock section provides a clock communication path between the baseband processing module and the RF circuit.

Abstract: Multi-concentric pad (MCP) arrangements provide for increased pad densities on integrated circuits. The multi-concentric pad (MCP) configuration includes a first set of input output (IO) pads and a second set of IO pads, both disposed on an integrated circuit die. Each IO pad in said first set and said second set of IO pads includes a bond pad for receiving a bond wire connection, and an IO circuit coupled to the bond pad. The IO circuits provide an interface between a signal received at the corresponding bond pad and a core circuit disposed on said IC die. The first set of IO pads are arranged closer to the perimeter of the IC die than the second set of IO pads. Furthermore, the second set of IO pads are arranged so that each IO circuit in the second set of IO pads is closer to the center of the IC die than a corresponding IO circuit in the first set of IO pads.

Abstract: A radio frequency (RF) integrated circuit (IC) operable to support wireless communications is provided. In one embodiment, the RF IC includes an advanced high-performance (AHB) bus matrix, a microprocessor core coupled to the AHB bus matrix, a plurality of processing modules wherein each processing module is operable to support one or more functions of the RF IC, and a plurality of power islands. Each power island is associated with one or more functions of the RF IC. This arrangement allows power islands coupled to the processing modules associated with the one or more functions associated with the power island to supply power for the processing modules associated with the one or more functions associated with the power island. Power from the power island(s) to the processing module(s) may be reduced or secured when the one or more functions associated with the power island is not required.

Abstract: A radio frequency (RF) integrated circuit (IC) operable to support wireless communications is provided. This RF IC includes a number of master components, a number of slave components, and a direct master slave bus. The master components may include a number of processing modules where each processing module is operable to support one or more functions of the RF IC. The direct master slave bus may couple at least one master component to at least one slave component based on mode of operation of the RF IC.