Patents by Inventor Vajeed Nimran

Vajeed Nimran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11831283
    Abstract: The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: November 28, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vajeed Nimran, Raja Sekhar, Sandeep Oswal, Shagun Dusad
  • Patent number: 11740208
    Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: August 29, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prashuk Jain, Ravikumar Pattipaka, Vajeed Nimran Parambil Abdul Raheem, Sandeep Kesrimal Oswal
  • Patent number: 11662448
    Abstract: Methods and apparatus for reducing a transient glitch in ultrasound applications are disclosed. An example apparatus includes a transducer to (A) output a signal during a transmit phase and (B) receive a reflected signal corresponding to the signal during a receive phase; a receiver switch coupled to the transducer at a first node, the receiver switch to (A) open during the transmit phase and (B) close during the receive phase; and a clamp coupled to the transducer at the first node, the clamp to provide a high impedance during the transmit phase and the receive phase and provide a low impedance during a transient phase.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: May 30, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ravikumar Pattipaka, Raja Sekhar Kanakamedala, Aravind Miriyala, Vajeed Nimran P A, Sandeep Kesrimal Oswal
  • Publication number: 20220011420
    Abstract: Methods and apparatus for reducing a transient glitch in ultrasound applications are disclosed. An example apparatus includes a transducer to (A) output a signal during a transmit phase and (B) receive a reflected signal corresponding to the signal during a receive phase; a receiver switch coupled to the transducer at a first node, the receiver switch to (A) open during the transmit phase and (B) close during the receive phase; and a clamp coupled to the transducer at the first node, the clamp to provide a high impedance during the transmit phase and the receive phase and provide a low impedance during a transient phase.
    Type: Application
    Filed: September 28, 2021
    Publication date: January 13, 2022
    Inventors: RAVIKUMAR PATTIPAKA, RAJA SEKHAR KANAKAMEDALA, ARAVIND MIRIYALA, VAJEED NIMRAN P A, SANDEEP KESRIMAL OSWAL
  • Patent number: 11163046
    Abstract: Methods and apparatus for reducing a transient glitch in ultrasound applications are disclosed. An example apparatus includes a transducer to (A) output a signal during a transmit phase and (B) receive a reflected signal corresponding to the signal during a receive phase; a receiver switch coupled to the transducer at a first node, the receiver switch to (A) open during the transmit phase and (B) close during the receive phase; and a clamp coupled to the transducer at the first node, the clamp to provide a high impedance during the transmit phase and the receive phase and provide a low impedance during a transient phase.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: November 2, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ravikumar Pattipaka, Raja Sekhar Kanakamedala, Aravind Miriyala, Vajeed Nimran P A, Sandeep Kesrimal Oswal
  • Publication number: 20210310996
    Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 7, 2021
    Inventors: Prashuk JAIN, Ravikumar PATTIPAKA, Vajeed Nimran PARAMBIL ABDUL RAHEEM, Sandeep Kesrimal OSWAL
  • Patent number: 11067544
    Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 20, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prashuk Jain, Ravikumar Pattipaka, Vajeed Nimran Parambil Abdul Raheem, Sandeep Kesrimal Oswal
  • Publication number: 20210211102
    Abstract: The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.
    Type: Application
    Filed: March 23, 2021
    Publication date: July 8, 2021
    Inventors: Vajeed Nimran, Raja Sekhar, Sandeep Oswal, Shagun Dusad
  • Patent number: 10985708
    Abstract: The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: April 20, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vajeed Nimran, Raja Sekhar, Sandeep Oswal, Shagun Dusad
  • Publication number: 20200256970
    Abstract: Methods and apparatus for reducing a transient glitch in ultrasound applications are disclosed. An example apparatus includes a transducer to (A) output a signal during a transmit phase and (B) receive a reflected signal corresponding to the signal during a receive phase; a receiver switch coupled to the transducer at a first node, the receiver switch to (A) open during the transmit phase and (B) close during the receive phase; and a clamp coupled to the transducer at the first node, the clamp to provide a high impedance during the transmit phase and the receive phase and provide a low impedance during a transient phase.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: RAVIKUMAR PATTIPAKA, RAJA SEKHAR KANAKAMEDALA, ARAVIND MIRIYALA, VAJEED NIMRAN P A, SANDEEP KESRIMAL OSWAL
  • Patent number: 10677903
    Abstract: Methods and apparatus for reducing a transient glitch in ultrasound applications are disclosed. An example apparatus includes a transducer to (A) output a signal during a transmit phase and (B) receive a reflected signal corresponding to the signal during a receive phase; a receiver switch coupled to the transducer at a first node, the receiver switch to (A) open during the transmit phase and (B) close during the receive phase; and a clamp coupled to the transducer at the first node, the clamp to provide a high impedance during the transmit phase and the receive phase and provide a low impedance during a transient phase.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: June 9, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ravikumar Pattipaka, Raja Sekhar Kanakamedala, Aravind Miriyala, Vajeed Nimran P A, Sandeep Kesrimal Oswal
  • Publication number: 20200129152
    Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.
    Type: Application
    Filed: December 14, 2018
    Publication date: April 30, 2020
    Inventors: Prashuk JAIN, Ravikumar PATTIPAKA, Vajeed Nimran PARAMBIL ABDUL RAHEEM, Sandeep Kesrimal OSWAL
  • Patent number: 10583461
    Abstract: A semiconductor device includes a trim storage and an encoder. The trim storage stores trim values. The encoder determines a magnitude of a supply voltage, determines a magnitude of a handle voltage, determines a source-to-handle voltage of a first transistor, and determines a source-to-handle voltage of a second transistor. Further, the encoder determines a target number of selectable first transistor units comprising the first transistor to select for the first transistor. Based on a trim value from the trim storage, the source-to-handle voltage of the first transistor and the source-to-handle voltage of the second transistor, the encoder determines a target number of selectable second transistor units comprising the second transistor to select for the second transistor. The encoder asserts control signals to select the target number of selectable first transistor units and the target number of selectable second transistor units.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: March 10, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind Miriyala, Naveen Kumar Ginige, Vajeed Nimran, Saugata Datta, Shabbir Amjhera Wala
  • Patent number: 10573292
    Abstract: A passive beamformer for ultrasound imaging. An ultrasound probe includes a plurality of ultrasound transducers and beamforming circuitry. Each of the ultrasound transducers is configured to convert ultrasonic signal into electrical signal. The beamforming circuitry is coupled to the plurality of ultrasound transducers. The beamforming circuitry includes a plurality of passive delay circuits and a passive hold circuit. One of the passive delay circuits is coupled to each of the ultrasound transducers. The passive hold circuit is coupled to the passive delay circuits to store a sum of the charges received from the delay circuits.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: February 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ravikumar Pattipaka, Vajeed Nimran, Sandeep Oswal
  • Patent number: 10367479
    Abstract: The disclosure provides a circuit that includes an integrator that generates an integrated signal in response to a current signal. A comparator is coupled to the integrator and receives the integrated signal and a primary reference voltage signal. The comparator generates a feedback signal. A switched capacitor network is coupled across the integrator. The feedback signal activates the switched capacitor network.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: July 30, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rahul Sharma, Vajeed Nimran, Jagannathan Venkataraman, Sandeep Kesrimal Oswal
  • Publication number: 20190009301
    Abstract: A semiconductor device includes a trim storage and an encoder. The trim storage stores trim values. The encoder determines a magnitude of a supply voltage, determines a magnitude of a handle voltage, determines a source-to-handle voltage of a first transistor, and determines a source-to-handle voltage of a second transistor. Further, the encoder determines a target number of selectable first transistor units comprising the first transistor to select for the first transistor. Based on a trim value from the trim storage, the source-to-handle voltage of the first transistor and the source-to-handle voltage of the second transistor, the encoder determines a target number of selectable second transistor units comprising the second transistor to select for the second transistor. The encoder asserts control signals to select the target number of selectable first transistor units and the target number of selectable second transistor units.
    Type: Application
    Filed: December 22, 2017
    Publication date: January 10, 2019
    Inventors: Aravind MIRIYALA, Naveen Kumar GINIGE, Vajeed NIMRAN, Saugata DATTA, Shabbir AMJHERA WALA
  • Publication number: 20180269856
    Abstract: The disclosure provides a circuit that includes an integrator that generates an integrated signal in response to a current signal. A comparator is coupled to the integrator and receives the integrated signal and a primary reference voltage signal. The comparator generates a feedback signal. A switched capacitor network is coupled across the integrator. The feedback signal activates the switched capacitor network.
    Type: Application
    Filed: May 16, 2018
    Publication date: September 20, 2018
    Inventors: Rahul Sharma, Vajeed Nimran, Jagannathan Venkataraman, Sandeep Kesrimal Oswal
  • Publication number: 20180262169
    Abstract: The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.
    Type: Application
    Filed: May 16, 2018
    Publication date: September 13, 2018
    Inventors: Vajeed Nimran, Raja Sekhar, Sandeep Oswal, Shagun Dusad
  • Publication number: 20180156903
    Abstract: Methods and apparatus for reducing a transient glitch in ultrasound applications are disclosed. An example apparatus includes a transducer to (A) output a signal during a transmit phase and (B) receive a reflected signal corresponding to the signal during a receive phase; a receiver switch coupled to the transducer at a first node, the receiver switch to (A) open during the transmit phase and (B) close during the receive phase; and a clamp coupled to the transducer at the first node, the clamp to provide a high impedance during the transmit phase and the receive phase and provide a low impedance during a transient phase.
    Type: Application
    Filed: December 2, 2016
    Publication date: June 7, 2018
    Inventors: RAVIKUMAR PATTIPAKA, RAJA SEKHAR KANAKAMEDALA, ARAVIND MIRIYALA, VAJEED NIMRAN P A, SANDEEP KESRIMAL OSWAL
  • Publication number: 20180137853
    Abstract: A passive beamformer for ultrasound imaging. An ultrasound probe includes a plurality of ultrasound transducers and beamforming circuitry. Each of the ultrasound transducers is configured to convert ultrasonic signal into electrical signal. The beamforming circuitry is coupled to the plurality of ultrasound transducers. The beamforming circuitry includes a plurality of passive delay circuits and a passive hold circuit. One of the passive delay circuits is coupled to each of the ultrasound transducers. The passive hold circuit is coupled to the passive delay circuits to store a sum of the charges received from the delay circuits.
    Type: Application
    Filed: October 13, 2017
    Publication date: May 17, 2018
    Inventors: Ravikumar PATTIPAKA, Vajeed NIMRAN, Sandeep OSWAL