Patents by Inventor Valentin Gherman

Valentin Gherman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8566679
    Abstract: An error-correcting coding method generates code words of m bits from useful data blocks of n bits. The method adds k check bits to a block of n useful data bits in order to generate a code word of m=n+k bits, said check bits being defined according to the combination rules defined by a parity matrix H consisting of binary elements and having k rows and m columns such that H·V=0, V being a column matrix whose m elements are the m bits of the code word to be generated. The k check bits are separated into two groups, on the one hand a group of k1 bits called total parity bits PT and on the other hand a group of k2 bits called conventional check bits VC, the values of k, k1 and k2 satisfying the conditions k=k1+k2 and k>k1>2, the matrix H whose columns can be swapped being broken down into six submatrices A, B, C, D, E and F. Another method detects multiple errors in code words generated by the coding method.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: October 22, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Valentin Gherman, Samuel Evain
  • Publication number: 20130103991
    Abstract: A method for protecting digital memory against permanent and transient errors and a related device, the digital data being stored in at least one storage matrix of memory cells in a given number of rows and columns, comprises: an encoding step generating code words from data organized in binary words by application of asymmetric code introducing at least two different levels of protection, the first level of protection said to be high being associated with a first sub-group of bits of the code word and a second level of protection said to be low being associated with a second sub-group of the same word; swapping positions of the bits of the code word making the bits with a high level of protection correspond for their storage to the columns of the storage area comprising defective memory cells and the bits with a low level of protection to the remaining columns.
    Type: Application
    Filed: June 1, 2011
    Publication date: April 25, 2013
    Inventors: Samuel Evain, Yannick Bonhomme, Valentin Gherman
  • Publication number: 20120110409
    Abstract: An error-correcting coding method generates code words of m bits from useful data blocks of n bits. The method adds k check bits to a block of n useful data bits in order to generate a code word of m=n+k bits, said check bits being defined according to the combination rules defined by a parity matrix H consisting of binary elements and having k rows and m columns such that H·V=0, V being a column matrix whose m elements are the m bits of the code word to be generated. The k check bits are separated into two groups, on the one hand a group of k1 bits called total parity bits PT and on the other hand a group of k2 bits called conventional check bits VC, the values of k, k1 and k2 satisfying the conditions k=k1+k2 and k>k1>2, the matrix H whose columns can be swapped being broken down into six submatrices A, B, C, D, E and F. Another method detects multiple errors in code words generated by the coding method.
    Type: Application
    Filed: February 1, 2010
    Publication date: May 3, 2012
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Valentin Gherman, Samuel Evain