Patents by Inventor Valerie L. Lines
Valerie L. Lines has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6667924Abstract: A signal detection circuit that provides multilevel sense detection that is both fast and has low power consumption. The signal detection circuit has amplifying means for providing at least one output corresponding to the difference in voltage levels between a sense node and a reference node. Input means apply a voltage level onto the sense node, and reference means apply a reference voltage onto the reference node. The input and reference means have substantially similar electrical characteristics, however, the reference means includes a reference device that is physically larger than a corresponding device of the input means.Type: GrantFiled: December 10, 2002Date of Patent: December 23, 2003Assignee: Mosaid Technologies IncorporatedInventors: Abdullah Ahmed, Valerie L. Lines
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Patent number: 6614705Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.Type: GrantFiled: March 28, 2001Date of Patent: September 2, 2003Assignee: Mosaid Technologies, Inc.Inventors: Richard C. Foss, Peter B. Gillingham, Robert F. Harland, Valerie L. Lines
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Patent number: 6608788Abstract: An architecture and method for fast precharge of bitlines in a densely packed, dynamic content addressable memory is disclosed. The dynamic content addressable memory cells are arranged according to an open bitline architecture to obtain high packing density. The bitlines are precharged through equalization between every two adjacent open bitline pairs. More specifically, a bitline and its adjacent neighboring bitline on the same side of the bitline sense amplifiers are equalized at several locations along the bitlines such that they are equalized at high speed, which is typically not available in open bitline architectures. Hence the adjacent bitlines are precharged in a manner similar to a folded bitline architecture. Additional equalization circuits are connected between the complementary bitlines of each open bitline pair, therefore during the precharge phase, all four bitlines of the two open bitline pairs are equalized with each other.Type: GrantFiled: November 8, 2002Date of Patent: August 19, 2003Assignee: Mosaid Technologies IncorporatedInventors: Peter P Ma, Abdullah Ahmed, Valerie L Lines
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Patent number: 6603703Abstract: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained.Type: GrantFiled: July 31, 2001Date of Patent: August 5, 2003Assignee: MOSAID Technologies, Inc.Inventor: Valerie L. Lines
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Patent number: 6580654Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.Type: GrantFiled: January 24, 2002Date of Patent: June 17, 2003Assignee: Mosaid Technologies, Inc.Inventors: Richard C. Foss, Peter B. Gillingham, Robert F. Harland, Valerie L. Lines
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Publication number: 20030081474Abstract: A signal detection circuit that provides multilevel sense detection that is both fast and has low power consumption. The signal detection circuit has amplifying means for providing at least one output corresponding to the difference in voltage levels between a sense node and a reference node. Input means apply a voltage level onto the sense node, and reference means apply a reference voltage onto the reference node. The input and reference means have substantially similar electrical characteristics, however, the reference means includes a reference device that is physically larger than a corresponding device of the input means.Type: ApplicationFiled: December 10, 2002Publication date: May 1, 2003Inventors: Abdullah Ahmed, Valerie L. Lines
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Publication number: 20030072205Abstract: An architecture and method for fast precharge of bitlines in a densely packed, dynamic content addressable memory is disclosed. The dynamic content addressable memory cells are arranged according to an open bitline architecture to obtain high packing density. The bitlines are precharged through equalization between every two adjacent open bitline pairs. More specifically, a bitline and its adjacent neighbouring bitline on the same side of the bitline sense amplifiers are equalized at several locations along the bitlines such that they are equalized at high speed, which is typically not available in open bitline architectures. Hence the adjacent bitlines are precharged in a manner similar to a folded bitline architecture. Additional equalization circuits are connected between the complementary bitlines of each open bitline pair, therefore during the precharge phase, all four bitlines of the two open bitline pairs are equalized with each other.Type: ApplicationFiled: November 8, 2002Publication date: April 17, 2003Inventors: Peter P. Ma, Abdullah Ahmed, Valerie L. Lines
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Patent number: 6538947Abstract: A method for detecting n match conditions within a CAM array. The method consists of precharging a sense node and a reference node of a differential amplifier in an inactive state to a supply voltage level. The reference node voltage level is then changed to a reference voltage level between a voltage level corresponding to n match condition signals and n−1 match condition signals by turning on a reference device, The sense node voltage level is changed to a voltage level corresponding to a number of match condition signals by turning on a corresponding number of matchline devices, and the reference voltage level is compared to the voltage level corresponding to the number of match condition signals by switching the differential amplifier to an active state. An output signal corresponding to the result of the comparison is then provided from the differential amplifier. The method can further include a step of switching the differential amplifier to the inactive state when the output signal is provided.Type: GrantFiled: September 24, 2001Date of Patent: March 25, 2003Assignee: Mosaid Technologies IncorporatedInventors: Abdullah Ahmed, Valerie L. Lines
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Publication number: 20030016580Abstract: An architecture and method for fast precharge of bitlines in a densely packed, dynamic content addressable memory is disclosed. The dynamic content addressable memory cells are arranged according to an open bitline architecture to obtain high packing density. The bitlines are precharged through equalization between every two adjacent open bitline pairs. More specifically, a bitline and its adjacent neighbouring bitline on the same side of the bitline sense amplifiers are equalized at several locations along the bitlines such that they are equalized at high speed, which is typically not available in open bitline architectures. Hence the adjacent bitlines are precharged in a manner similar to a folded bitline architecture. Additional equalization circuits are connected between the complementary bitlines of each open bitline pair, therefore during the precharge phase, all four bitlines of the two open bitline pairs are equalized with each other.Type: ApplicationFiled: September 21, 2001Publication date: January 23, 2003Inventors: Peter P. Ma, Abdullah Ahmed, Valerie L. Lines
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Patent number: 6504775Abstract: An architecture and method for fast precharge of bitlines in a densely packed, dynamic content addressable memory is disclosed. The dynamic content addressable memory cells are arranged according to an open bitline architecture to obtain high packing density. The bitlines are precharged through equalization between every two adjacent open bitline pairs. More specifically, a bitline and its adjacent neighbouring bitline on the same side of the bitline sense amplifiers are equalized at several locations along the bitlines such that they are equalized at high speed, which is typically not available in open bitlines architectures. Hence the adjacent bitlines are precharged in a manner similar to a folded bitline architecture. Additional equalization circuits are connected between the complementary bitlines of each open bitline pair, therefore during the precharge phase, all four bitlines of the two open bitline pairs are equalized with each other.Type: GrantFiled: September 21, 2001Date of Patent: January 7, 2003Assignee: Mosaid Technologies Incorporated KanataInventors: Peter P Ma, Abdullah Ahmed, Valerie L Lines
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Publication number: 20020075706Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.Type: ApplicationFiled: January 24, 2002Publication date: June 20, 2002Applicant: MOSAID Technologies IncorporatedInventors: Richard C. Foss, Peter B. Gillingham, Robert F. Harland, Valerie L. Lines
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Publication number: 20020042865Abstract: A system and method for high speed generation of a global address corresponding to the highest priority active matchline sense output signal received after a CAM search-and-compare operation is disclosed. A priority encoder having blocks of multiple match resolver circuits arranged in a logical order of priority receives a plurality of active matchline sense output signals. Each block of multiple match resolver circuits generates a flag signal and a local address corresponding to the highest priority active matchline sense output signal received. Control logic receives flag signals from the multiple match resolver circuits, and identifies the highest priority multiple match resolver circuit that has received an active matchline sense output signal. The control logic then disables all lower priority multiple match resolver circuits such that only the local address generated by the highest priority multiple match resolver circuit is passed by the priority encoder.Type: ApplicationFiled: September 18, 2001Publication date: April 11, 2002Inventors: Robert N. McKenzie, Valerie L. Lines
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Publication number: 20020009009Abstract: The invention detects multiple matches between search and stored data in high-density content addressable memories. An input signal is derived from the matchlines, such that the input signal starts discharging form a predetermined precharge level towards a discharge level determined by the number of match conditions. A reference signal is generated such that it starts to discharge at the same time from the same precharge level towards a reference level which falls between the two discharge levels corresponding to single and double match condition. A latching differential amplifier is activated shortly thereafter to compare the input signal with the reference signal and thereby provide an indication whether a multiple single or no match occurs on the matchlines, after which the amplifier is deactivated. The disclosed circuit features a relatively fast detection with low current consumption.Type: ApplicationFiled: September 24, 2001Publication date: January 24, 2002Inventors: Abdullah Ahmed, Valerie L. Lines
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Publication number: 20010046162Abstract: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained.Type: ApplicationFiled: July 31, 2001Publication date: November 29, 2001Applicant: MOSAID Technologies Incorporated KanataInventor: Valerie L. Lines
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Patent number: 6307798Abstract: The invention detects multiple matches between search and stored data in high-density content addressable memories. An input signal is derived from the matchlines, such that the input signal starts discharging form a predetermined precharge level towards a discharge level determined by the number of match conditions. A reference signal is generated such that it starts to discharge at the same time from the same precharge level towards a reference level which falls between the two discharge levels corresponding to single and double match condition. A latching differential amplifier is activated shortly thereafter to compare the input signal with the reference signal and thereby provide an indication whether a multiple single or no match occurs on the matchlines, after which the amplifier is deactivated. The disclosed circuit features a relatively fast detection with low current consumption.Type: GrantFiled: April 24, 2000Date of Patent: October 23, 2001Assignee: Mosaid Technologies IncorporatedInventors: Abdullah Ahmed, Valerie L. Lines
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Patent number: 6278640Abstract: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained.Type: GrantFiled: April 13, 2000Date of Patent: August 21, 2001Assignee: Mosaid Technologies IncorporatedInventor: Valerie L. Lines
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Publication number: 20010009518Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by Vtn as in the prior art. The boosting capacitors are charged by Vdd, thus eliminating drift tracking problems associated with clock boosting sources and Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.Type: ApplicationFiled: March 28, 2001Publication date: July 26, 2001Applicant: MOSAID Technologies IncorporatedInventors: Richard C. Foss, Peter B. Gillingham, Robert F. Harland, Valerie L. Lines
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Patent number: 6236581Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by Vtn as in the prior art. The boosting capacitors are charged by Vdd, thus eliminating drift tracking problems associated with clock boosting sources and Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.Type: GrantFiled: January 14, 2000Date of Patent: May 22, 2001Assignee: Mosaid Technologies IncorporatedInventors: Richard C. Foss, Peter B. Gillingham, Robert F. Harland, Valerie L. Lines
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Patent number: 6061277Abstract: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM is comprised of word lines, memory cells having enable inputs connected to the word lines, apparatus for receiving word line selecting signals at first logic levels V.sub.ss and V.sub.dd, and for providing a select signal at levels V.sub.ss and V.sub.dd, a high voltage supply source V.sub.pp which is higher in voltage than V.sub.dd, a circuit for translating the select signals at levels V.sub.ss and V.sub.dd to levels V.sub.ss and V.sub.Type: GrantFiled: July 27, 1998Date of Patent: May 9, 2000Assignee: Mosaid Technologies IncorporatedInventor: Valerie L. Lines
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Patent number: 6055201Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.Type: GrantFiled: October 26, 1998Date of Patent: April 25, 2000Assignee: Mosaid Technologies IncorporatedInventors: Richard C. Foss, Peter B. Gillingham, Robert F. Harland, Valerie L. Lines