Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM is comprised of bit lines and word lines, memory cells connected to the bit lines and word lines, each memory cell being comprised of an access field effect transistor (FET) having its source-drain circuit connected between a bit line and a high logic level voltage V.sub.dd bit charge storage capacitor, the field effect transistor having a gate connected to a corresponding word line; a high V.sub.pp supply voltage source which is in excess of high logic level voltage V.sub.

Abstract: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, apparatus for receiving word line selecting signals at first logic levels V.sub.ss and V.sub.dd, and for providing a select signal at levels V.sub.ss and V.sub.dd, a high voltage supply source V.sub.pp which is higher in voltage than V.sub.dd, a circuit for translating the select signals at levels V.sub.ss and V.sub.dd to levels V.sub.ss and V.sub.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating draft tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: A method and apparatus for precharging memory cell bit storage capacitors and bit lines of a DRAM from a single source. The storage capacitor reference plate is driven from a high impedance voltage divider, minimizing the effects of voltage supply noise, so that noise does not couple into the storage capacitor and turn on the associated capacitor access transistor. At the same time the bit line is driven from a low impedance drive, to enable it to maintain the bit line midpoint voltage. The bit line precharge voltage is referenced to the storage capacitor reference voltage providing good cell margin.

Abstract: A DRAM row or column decoder having a fused stage for disabling defective rows or columns. A fuse is placed within a stage preceding the final output stage of a multi-stage row or column decoder. Because the fuse is not placed within the output stage, it is not necessary to have one fuse for each individual row or column; a single fuse can disable several decoder outputs, and thus several rows or columns can be disabled at the same time.

Abstract: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained A DRAM is comprised of bit lines and word lines, memory cells connected to the bit lines and word lines, each memory cell being comprised of an access field effect transistor (FET) having its source-drain circuit connected between a bit line and a high logic level voltage V.sub.dd bit charge storage capacitor, the field effect transistor having a gate connected to a corresponding word line; a high V.sub.pp supply voltage source which is in excess of high logic level voltage V.sub.