Patents by Inventor Valluri R. Rao

Valluri R. Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190297975
    Abstract: Embodiments of the invention include an active venting system. According to an embodiment of the invention, the active venting system may include a substrate having one or more seams formed through the substrate. In order to open the vents defined by the seams through the substrate, a piezoelectric layer may be formed proximate to one or more of the seams. Additional embodiments may include a first electrode and a second electrode that contact the piezoelectric layer in order to provide a voltage differential across the piezoelectric layer. In an embodiment the active venting system may be integrated into a garment. In such an embodiment, the garment may also include an electronics module for controlling the actuators. Additionally, conductive traces may be printed on the garment or sewn into the garment to provide electrical connections from the electronics module to each of the piezoelectric actuators.
    Type: Application
    Filed: July 2, 2016
    Publication date: October 3, 2019
    Inventors: Aleksandar ALEKSOV, Sasha N. OSTER, Feras EID, Shawna M. LIFF, Thomas L. SOUNART, Johanna M. SWAN, Baris BICEN, Valluri R. RAO
  • Patent number: 10432167
    Abstract: Embodiments of the invention include a piezoelectric resonator which includes an input transducer having a first piezoelectric material, a vibrating structure coupled to the input transducer, and an output transducer coupled to the vibrating structure. In one example, the vibrating structure is positioned above a cavity of an organic substrate. The output transducer includes a second piezoelectric material. In operation the input transducer causes an input electrical signal to be converted into mechanical vibrations which propagate across the vibrating structure to the output transducer.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Feras Eid, Baris Bicen, Telesphor Kamgaing, Vijay K. Nair, Johanna M. Swan, Georgios C. Dogiamis, Valluri R. Rao
  • Patent number: 10291283
    Abstract: Embodiments of the invention include a tunable radio frequency (RF) communication module that includes a transmitting component having at least one tunable component and a receiving component having at least one tunable component. The tunable RF communication module includes at least one piezoelectric switching device coupled to at least one of the transmitting and receiving components. The at least one piezoelectric switching device is formed within an organic substrate having organic material and is designed to tune at least one tunable component of the tunable RF communication module.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Feras Eid, Adel A. Elsherbini, Georgios C. Dogiamis, Vijay K. Nair, Johanna M. Swan, Valluri R. Rao
  • Publication number: 20190121038
    Abstract: Embodiments of the invention include an optoelectronic package that allows for in situ alignment of optical fibers. In an embodiment, the optoelectronic package may include an organic substrate. Embodiments include a cavity formed into the organic substrate. Additionally, the optoelectronic package may include an actuator formed on the organic substrate that extends over the cavity. In one embodiment, the actuator may include a first electrode, a piezoelectric layer formed on the first electrode, and a second electrode formed on the piezoelectric layer. According to an additional embodiment of the invention, the actuator may include a first portion and a second portion. In order to allow for resistive heating and actuation driven by thermal expansion, a cross-sectional area of the first portion of the beam may be greater than a cross-sectional area of the second portion of the beam.
    Type: Application
    Filed: July 1, 2016
    Publication date: April 25, 2019
    Inventors: Johanna M. SWAN, Aleksandar ALEKSOV, Sasha N. OSTER, Feras EID, Baris BICEN, Thomas L. SOUNART, Shawna M. LIFF, Valluri R. RAO
  • Patent number: 10256286
    Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 9, 2019
    Assignee: INTEL CORPORATION
    Inventors: Andreas Duevel, Telesphor Kamgaing, Valluri R. Rao, Uwe Zillmann
  • Publication number: 20190051562
    Abstract: This disclosure is directed to a complementary metal oxide semiconductor (CMOS) transistor that includes a gallium nitride n-type MOS and a silicon P-type MOS. The transistor includes silicon 111 substrate, a gallium nitride transistor formed in a trench in the silicon 111 substrate, the gallium nitride transistor comprising a source electrode, a gate electrode, and a drain electrode; a polysilicon layer formed on the gallium nitride transistor, the polysilicon layer coplanar with a top side of the silicon 111 substrate; a first metal via disposed on the source electrode; a second metal via disposed on the gate electrode and isolated from the first metal via by a polysilicon layer; a first trench contact formed on the first metal via; and a second trench contact formed on the second metal via; the first trench contact isolated from the second trench contact by at least one replacement metal gate (RMG) polysilicon island.
    Type: Application
    Filed: April 1, 2016
    Publication date: February 14, 2019
    Applicant: Intel Corporation
    Inventors: Marko Radosavljevic, Sansaptak Dasgupta, Valluri R. Rao, Han Wui Then
  • Publication number: 20190051650
    Abstract: This disclosure pertains to a gallium nitride transistor that is formed in a trench etched into a silicon substrate. A gallium nitride layer is on the trench of the silicon substrate. A source electrode and a drain electrode reside on the gallium nitride layer. A gate electrode resides on the gallium nitride layer between the source electrode and the drain electrode. A first polarization layer resides on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer resides on the gallium nitride layer between the gate electrode and the drain electrode. The silicon substrate can include a silicon 111 substrate.
    Type: Application
    Filed: March 28, 2016
    Publication date: February 14, 2019
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Peter G. Tolchinsky, Roza Kotlyar, Valluri R. Rao
  • Publication number: 20190032272
    Abstract: Embodiments of the invention include an active fiber with a piezoelectric layer that has a crystallization temperature that is greater than a melt or draw temperature of the fiber and methods of forming such active fibers. According to an embodiment, a first electrode is formed over an outer surface of a fiber. Embodiments may then include depositing a first amorphous piezoelectric layer over the first electrode. Thereafter, the first amorphous piezoelectric layer may be crystallized with a pulsed laser annealing process to form a first crystallized piezoelectric layer. In an embodiment, the pulsed laser annealing process may include exposing the first amorphous piezoelectric layer to radiation from an excimer laser with an energy density between approximately 10 and 100 mJ/cm2 and pulse width between approximately 10 and 50 nanoseconds. Embodiments may also include forming a second electrode over an outer surface of the crystallized piezoelectric layer.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 31, 2019
    Inventors: Shawna M. LIFF, Feras EID, Aleksandar ALEKSOV, Sasha N. OSTER, Baris BICEN, Thomas L. SOUNART, Valluri R. RAO, Johanna M. SWAN
  • Publication number: 20190033575
    Abstract: Embodiments of the invention include a piezo-electric mirror in an microelectronic package and methods of forming the package. According to an embodiment the microelectronic package may include an organic substrate with a cavity formed in the organic substrate. In some embodiments, an actuator is anchored to the organic substrate and extends over the cavity. For example, the actuator may include a first electrode and a piezo-electric layer formed on the first electrode. A second electrode may be formed on the piezo-electric layer. Additionally, a mirror may be formed on the actuator. Embodiments allow for the piezo-electric layer to be formed on an organic package substrate by using low temperature crystallization processes. For example, the piezo-electric layer may be deposited in an amorphous state. Thereafter, a laser annealing process that includes a pulsed laser may be used to crystallize the piezo-electric layer.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 31, 2019
    Inventors: Sasha N. OSTER, Feras EID, Johanna M. SWAN, Shawna M. LIFF, Aleksandar ALEKSOV, Thomas L. SOUNART, Baris BICEN, Valluri R. RAO
  • Publication number: 20190036002
    Abstract: Embodiments of the invention include piezoelectrically driven switches that are used for modifying a background color or light source color in display systems, and methods of forming such devices. In an embodiment, a piezoelectrically actuated switch for modulating a background color in a display may include a photonic crystal that has a plurality of blinds oriented substantially perpendicular to a surface of the display. In an embodiment, the blinds include a black surface and a white surface. The switch may also include an anchor spaced away from an edge of the photonic crystal and a piezoelectric actuator formed on the surface of the anchor and a surface of the photonic crystal. Some embodiments may include a photonic crystal that is a multi-layer polymeric structure or a polymer chain with a plurality of nanoparticles spaced at regular intervals on the polymer chain.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 31, 2019
    Inventors: Shawna M. LIFF, Feras EID, Aleksandar ALEKSOV, Sasha N. OSTER, Baris BICEN, Thomas L. SOUNART, Johanna M. SWAN, Adel A. ELSHERBINI, Valluri R. RAO
  • Publication number: 20190033500
    Abstract: Embodiments of the invention include an optical grating switch integrated into an organic substrate and methods of forming such devices. According to an embodiment, the optical grating switch may include a cavity formed into an organic substrate. Additionally, the optical grating switch may include an array of moveable beams anchored to the organic substrate and suspended over the cavity. In an embodiment of the invention, each of the moveable beams in the optical grating switch may include a piezoelectric region formed over end portions of the moveable beam and a top electrode formed over a top surface of each of the piezoelectric regions. In order to reflect or diffract light, embodiments of the invention may include moveable beams that include a reflective surface formed over a central portion of the moveable beam.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 31, 2019
    Inventors: Thomas L. SOUNART, Baris BICEN, Feras EID, Sasha N. OSTER, Aleksandar ALEKSOV, Shawna M. LIFF, Valluri R. RAO, Johanna M. SWAN
  • Publication number: 20190036004
    Abstract: Embodiments of the invention include a piezoelectric sensor system. According to an embodiment of the invention, the piezoelectric sensor system may include a piezoelectric sensor, a signal conditioning circuit, and a light source each formed on an organic or flexible substrate. In embodiments of the invention, the piezoelectric sensor may be a discrete component or the piezo electric sensor may be integrated into the substrate. According to an embodiment, a piezoelectric sensor that is integrated into the substrate may comprise, a cavity formed into the organic substrate and a moveable beam formed over the cavity and anchored to the organic substrate. Additionally, the piezoelectric sensor may include a piezoelectric region formed over an end portion of the moveable beam and extending at least partially over the cavity. The piezoelectric sensor may also include a top electrode formed over a top surface of the piezoelectric region.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 31, 2019
    Inventors: Feras EID, Sasha N. OSTER, Shawna M. LIFF, Johanna M. SWAN, Thomas L. SOUNART, Aleksandar ALEKSOV, Valluri R. RAO, Baris BICEN
  • Publication number: 20190033576
    Abstract: Embodiments of the invention include a display formed on an organic substrate and methods of forming such a device. According to an embodiment, an array of pixel mirrors may be formed on the organic substrate. For example, each of the pixel mirrors is actuatable about one or more axes out of the plane of the organic substrate. Additionally, embodiments of the invention may include an array of routing mirrors formed on the organic substrate. According to an embodiment, each of the routing mirrors is actuatable about two axes out of the plane of the organic substrate. In embodiments of the invention, a light source may be used for emitting light towards the array of routing mirrors. For example, light emitted from the light source may be reflected to one or more of the pixel mirrors by one of the routing mirrors.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 31, 2019
    Inventors: Sasha N. OSTER, Feras EID, Johanna M. SWAN, Thomas L. SOUNART, Aleksandar ALEKSOV, Shawna M. LIFF, Baris BICEN, Valluri R. RAO
  • Publication number: 20190025573
    Abstract: Embodiments of the invention include maskless imaging tools and display systems that include piezoelectrically actuated mirrors and methods of forming such devices. According to an embodiment, the maskless imaging tool may include a light source. Additionally, the tool may include one or more piezoelectrically actuated mirrors for receiving light from the light source. In an embodiment, the piezoelectrically actuated mirrors are actuatable about one or more axes to reflect the light from the light source to a workpiece positioned to receive light from the piezoelectrically actuated mirror. Additional embodiments of the invention may include a maskless imaging tool that is a laser direct imaging lithography (LDIL) tool. Other embodiments may include a maskless imaging tool that is a via-drill tool. Embodiments of the invention may also include a piezoelectrically actuated mirror used in a projection system. For example, the projection system may be integrated into a pair of glasses.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 24, 2019
    Inventors: Aleksandar ALEKSOV, Feras EID, Sasha N. OSTER, Shawna M. LIFF, Johanna M. SWAN, Thomas L. SOUNART, Baris BICEN, Valluri R. RAO
  • Publication number: 20190006171
    Abstract: Methods and devices integrating circuitry including both III-N (e.g., GaN) transistors and Si-based (e.g., Si or SiGe) transistors. In some monolithic wafer-level integration embodiments, a silicon-on-insulator (SOI) substrate is employed as an epitaxial platform providing a first silicon surface advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N transistors (e.g., III-N HFETs) are formed, and a second silicon surface advantageous for seeding an epitaxial raised silicon upon which Si-based transistors (e.g., Si FETs) are formed. In some heterogeneous wafer-level integration embodiments, an SOI substrate is employed for a layer transfer of silicon suitable for fabricating the Si-based transistors onto another substrate upon which III-N transistors have been formed. In some such embodiments, the silicon layer transfer is stacked upon a planar interlayer dielectric (ILD) disposed over one or more metallization level interconnecting a plurality of III-N HFETs into HFET circuitry.
    Type: Application
    Filed: August 28, 2015
    Publication date: January 3, 2019
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Ravi Pillarisetty, Kimin Jun, Patrick Morrow, Valluri R. Rao, Paul B. Fischer, Robert S. Chau
  • Patent number: 10134727
    Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Gerhard Schrom, Valluri R. Rao, Robert S. Chau
  • Patent number: 10070524
    Abstract: A glass core substrate for an integrated circuit (IC) device may be formed to include a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Qing Ma, Quan A. Tran, Robert L. Sankman, Johanna M. Swan, Valluri R. Rao
  • Patent number: 10032052
    Abstract: Embodiments of the invention include delay line circuitry that is integrated with an organic substrate. Organic dielectric material and a plurality of conductive layers form the organic substrate. The delay line circuitry includes a piezoelectric transducer to receive a guided electromagnetic wave signal and to generate an acoustic wave signal to be transmitted with an acoustic transmission medium. An acoustic reflector is communicatively coupled to the acoustic transmission medium. The acoustic reflector receives a plurality of acoustic wave signals from the acoustic transmission medium and reflects acoustic wave signals to the piezoelectric transducer using the acoustic transmission medium. The transducer converts the reflected acoustic signals into electromagnetic waves which are then transmitted back through the antenna and decoded by the reader.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Telesphor Kamgaing, Feras Eid, Vijay K. Nair, Georgios C. Dogiamis, Johanna M. Swan, Valluri R. Rao
  • Patent number: 9881990
    Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: January 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Andreas Duevel, Telesphor Kamgaing, Valluri R. Rao, Uwe Zillmann
  • Publication number: 20170309700
    Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.
    Type: Application
    Filed: May 8, 2017
    Publication date: October 26, 2017
    Inventors: Andreas DUEVEL, Telesphor KAMGAING, Valluri R. RAO, Uwe ZILLMANN