Abstract: An electronic assembly is assembling by stacking two or more integrated circuit dies on top of one another. An opening is formed into a lower portion of an upper die, and subsequently filled with a conductive member. The conductive member is located on a lower die, and the conductive member interconnects integrated circuits of the upper and lower dies. The opening is formed through a lower portion only of the upper die so that it does not take up “real estate” over reserved for metal layers of the integrated circuit. By making the opening after the integrated circuit is manufactured, the location of the conductive member can be customized after the integrated circuit is formed, and so provides more flexibility when interconnecting with dies from different manufacturers.

Abstract: A method including to a resonator coupled to at least one support structure on a substrate, the resonator having a resonating frequency in response to a frequency stimulus, modifying the resonating frequency by modifying the at least one support structure. A method including forming a resonator coupled to at least one support structure on a chip-level substrate, the resonator having a resonating frequency; and modifying the resonating frequency of the resonator by modifying the at least one support structure. A method including applying a frequency stimulus to a resonator coupled to at least one support structure on a chip-level substrate determining a resonating frequency; and modifying the resonating frequency of the resonator by modifying the at least one support structure.

Abstract: A method including to a resonator coupled to at least one support structure on a substrate, the resonator having a resonating frequency in response to a frequency stimulus, modifying the resonating frequency by modifying the at least one support structure. A method including forming a resonator coupled to at least one support structure on a chip-level substrate, the resonator having a resonating frequency; and modifying the resonating frequency of the resonator by modifying the at least one support structure. A method including applying a frequency stimulus to a resonator coupled to at least one support structure on a chip-level substrate determining a resonating frequency; and modifying the resonating frequency of the resonator by modifying the at least one support structure.

Abstract: A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substrate to send a clock signal to clock an area of the integrated circuit.

Abstract: A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substrate to send a clock signal to clock an area of the integrated circuit.

Abstract: A flip-chip having a decoupling capacitor electrically coupled to the backside thereof. The flip-chip includes a semiconductor substrate having first and second opposing surfaces with circuit elements formed within the first surface. A plurality of raised bump contacts are located on the first surface and connected to the circuit elements. A plurality of electrical interconnects are also located on or within the second surface and connected to the circuit elements. The electrodes of a decoupling capacitor are electrically coupled to the plurality of electrical interconnects.

Abstract: An apparatus is disclosed. In one embodiment, the apparatus includes a semiconductor substrate and a second substrate. The semiconductor substrate has a top side and a bottom side. The semiconductor substrate has an integrated circuit and at least one alignment fiducial formed on the top side. The alignment fudicial is aligned with the integrated circuit and the alignment fiducial is accessible from the bottom side. The semiconductor substrate further includes a first set of bond pads on the integrated circuit, the bond pads on the top side. The second substrate has a second set of bond pads corresponding to the first set of bond pads. The semiconductor substrate is coupled to the second substrate at a plurality of solder interconnections disposed between the first and the second set of bond pads.

Abstract: A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substrate to send a clock signal to clock an area of the integrated circuit.

Abstract: A method for accessing a portion of an integrated circuit formed on top of a semiconductor substrate from the bottom of the semiconductor substrate. First, alignment marks are located which are approximately aligned to the integrated circuit. These alignment marks are then used in conjunction with a circuit diagram of the integrated circuit to determine the point on the bottom of the semiconductor substrate residing beneath the portion of the integrated circuit which the practitioner desires to access. Finally, an opening is etched into the bottom of the semiconductor substrate at this point.

Abstract: A method and an apparatus for detecting an electric field in the active regions of an integrated circuit disposed in a semiconductor. In one embodiment, a laser beam is operated at a wavelength near the band gap of a semiconductor such as silicon. The laser beam is focused onto a P-N junction, such as for example the drain of an MOS transistor, through the back side of the semiconductor substrate. As a result of photo-absorption, the laser beam is partially absorbed in the P-N junction. When an external electric field is impressed on the P-N junction, such as when for example the drain of the transistor switches, the degree of photo-absorption will be modulated in accordance with the modulation in the electric field due to the phenomenon of electro-absorption. Electro-absorption also leads to electro-refraction which leads to a modulation in the reflection coefficient for the light reflected from the P-N junction/oxide interface.

Abstract: An integrated circuit device having alignment marks that are located on the integrated circuit device semiconductor substrate and aligned to the integrated circuit. The alignment marks are used in conjunction with a circuit diagram of the integrated circuit to determine the point on the bottom of the semiconductor substrate residing beneath the portion of the integrated circuit which the practitioner desires to access.