Patents by Inventor Vamsi Paruchuri
Vamsi Paruchuri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047197Abstract: Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.Type: ApplicationFiled: October 20, 2023Publication date: February 8, 2024Inventors: Jan Willem Hub Maes, Michael Eugene Givens, Suvi P. Haukka, Vamsi Paruchuri, Ivo Johannes Raaijmakers, Shaoren Deng, Andrea Illiberi, Eva E. Tois, Delphine Longrie, Viljami J. Pore
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Patent number: 11830732Abstract: Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.Type: GrantFiled: September 9, 2021Date of Patent: November 28, 2023Assignee: ASM IP Holding B.V.Inventors: Jan Willem Hub Maes, Michael Eugene Givens, Suvi P. Haukka, Vamsi Paruchuri, Ivo Johannes Raaijmakers, Shaoren Deng, Andrea Illiberi, Eva E. Tois, Delphine Longrie, Viljami Pore
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Publication number: 20220208542Abstract: Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.Type: ApplicationFiled: September 9, 2021Publication date: June 30, 2022Inventors: Jan Willem Hub Maes, Michael Eugene Givens, Suvi P. Haukka, Vamsi Paruchuri, Ivo Johannes Raaijmakers, Shaoren Deng, Andrea Illiberi, Eva E. Tois, Delphine Longrie
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Publication number: 20210371978Abstract: Direct liquid injection systems and vapor deposition systems including direct liquid injection systems are disclosed. Exemplary direct liquid injection systems and related vapor deposition systems can be configured for forming vanadium containing layer on a substrate by cyclical deposition processes.Type: ApplicationFiled: May 25, 2021Publication date: December 2, 2021Inventors: Eric James Shero, Dieter Pierreux, Bert Jongbloed, Werner Knaepen, Charles Dezelah, Qi Xie, Petri Raisanen, Hannu A. Huotari, Paul Ma, Vamsi Paruchuri
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Publication number: 20210358745Abstract: Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.Type: ApplicationFiled: July 30, 2021Publication date: November 18, 2021Inventors: Jan Willem Maes, Michael Eugene Givens, Suvi P. Haukka, Vamsi Paruchuri, Ivo Johannes Raaijmakers, Shaoren Deng, Andrea Illiberi, Eva E. Tois, Delphine Longrie, Charles Dezelah, Marko Tuominen
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Patent number: 11145506Abstract: Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.Type: GrantFiled: September 30, 2019Date of Patent: October 12, 2021Assignee: ASM IP HOLDING B.V.Inventors: Jan Willem Hub Maes, Michael Eugene Givens, Suvi P. Haukka, VamsI Paruchuri, Ivo Johannes Raaijmakers, Shaoren Deng, Andrea Illiberi, Eva E. Tois, Delphine Longrie
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Publication number: 20200105515Abstract: Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.Type: ApplicationFiled: September 30, 2019Publication date: April 2, 2020Applicant: ASM IP Holding B.V.Inventors: Jan Willem Hub Maes, Michael Eugene Givens, Suvi P. Haukka, Vamsi Paruchuri, Ivo Johannes Raaijmakers, Shaoren Deng, Andrea Illiberi, Eva E. Tois, Delphine Longrie
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Patent number: 9305883Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.Type: GrantFiled: February 12, 2015Date of Patent: April 5, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Sebastian Naczas, Vamsi Paruchuri, Alexander Reznicek, Dominic J. Schepis
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Publication number: 20150179576Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.Type: ApplicationFiled: February 12, 2015Publication date: June 25, 2015Inventors: Sebastian Naczas, Vamsi Paruchuri, Alexander Reznicek, Dominic J. Schepis
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Patent number: 9054109Abstract: A method of producing reduced corrosion interconnect structures and structures thereby formed. A method of producing microelectronic interconnects having reduced corrosion begins with a damascene structure having a first dielectric and a first interconnect. A metal oxide layer is deposited selectively to metal or nonselective over the damascene structure and then thermally treated. The treatment converts the metal oxide over the first dielectric to a metal silicate while the metal oxide over the first interconnect remains as a self-aligned protective layer. When a subsequent dielectric stack is formed and patterned, the protective layer acts as an etch stop, oxidation barrier and ion bombardment protector. The protective layer is then removed from the patterned opening and a second interconnect formed. In a preferred embodiment the metal oxide is a manganese oxide and the metal silicate is a MnSiCOH, the interconnects are substantially copper and the dielectric contains ultra low-k.Type: GrantFiled: May 29, 2012Date of Patent: June 9, 2015Assignee: International Business Machines CorporationInventors: Wei Lin, Son Nguyen, Vamsi Paruchuri, Tuan A. Vo
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Patent number: 9053926Abstract: Embodiments include methods of forming dielectric layers. According to an exemplary embodiment, a dielectric layer may be formed by determining a desired thickness of the dielectric layer, forming a first dielectric sub-layer having a thickness less than the desired thickness by depositing a first metal layer above a substrate and oxidizing the first metal layer, and forming n (where n is greater than 1) additional dielectric sub-layers having a thickness less than the desired thickness above the first dielectric sub-layer by the same method of the first dielectric sub-layer so that a combined thickness of all dielectric sub-layers is approximately equal to the desired thickness.Type: GrantFiled: March 18, 2013Date of Patent: June 9, 2015Assignees: International Business Machines Corporation, Canon Anelva CorporationInventors: Paul Jamison, Juntao Li, Vamsi Paruchuri, Tuan A. Vo, Takaaki Tsunoda, Sanjay Shinde
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Patent number: 8999779Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.Type: GrantFiled: September 6, 2013Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Sebastian Naczas, Vamsi Paruchuri, Alexander Reznicek, Dominic J. Schepis
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Publication number: 20150069531Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.Type: ApplicationFiled: September 6, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: Sebastian Naczas, Vamsi Paruchuri, Alexander Reznicek, Dominic J. Schepis
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Publication number: 20140273425Abstract: Embodiments include methods of forming dielectric layers. According to an exemplary embodiment, a dielectric layer may be formed by determining a desired thickness of the dielectric layer, forming a first dielectric sub-layer having a thickness less than the desired thickness by depositing a first metal layer above a substrate and oxidizing the first metal layer, and forming n (where n is greater than 1) additional dielectric sub-layers having a thickness less than the desired thickness above the first dielectric sub-layer by the same method of the first dielectric sub-layer so that a combined thickness of all dielectric sub-layers is approximately equal to the desired thickness.Type: ApplicationFiled: March 18, 2013Publication date: September 18, 2014Applicants: CANON ANELVA CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Jamison, Juntao Li, Vamsi Paruchuri, Tuan A. Vo, Takaaki Tsunoda, Sanjay Shinde
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Publication number: 20130320544Abstract: A method of producing reduced corrosion interconnect structures and structures thereby formed. A method of producing microelectronic interconnects having reduced corrosion begins with a damascene structure having a first dielectric and a first interconnect. A metal oxide layer is deposited selectively to metal or nonselective over the damascene structure and then thermally treated. The treatment converts the metal oxide over the first dielectric to a metal silicate while the metal oxide over the first interconnect remains as a self-aligned protective layer. When a subsequent dielectric stack is formed and patterned, the protective layer acts as an etch stop, oxidation barrier and ion bombardment protector. The protective layer is then removed from the patterned opening and a second interconnect formed. In a preferred embodiment the metal oxide is a manganese oxide and the metal silicate is a MnSiCOH, the interconnects are substantially copper and the dielectric contains ultra low-k.Type: ApplicationFiled: May 29, 2012Publication date: December 5, 2013Applicant: International Business Machines CorporationInventors: Wei Lin, Son Nguyen, Vamsi Paruchuri, Tuan A. Vo
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Patent number: 8187961Abstract: A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.Type: GrantFiled: August 4, 2009Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Eduard Albert Cartier, Vijay Narayanan, Vamsi Paruchuri
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Patent number: 8183642Abstract: CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.Type: GrantFiled: February 2, 2011Date of Patent: May 22, 2012Assignee: International Business Machines CorporationInventors: Dae-Gyu Park, Michael P Chudzik, Rashmi Jha, Siddarth A Krishnan, Naim Moumen, Vijay Narayanan, Vamsi Paruchuri
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Patent number: 8030716Abstract: A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.Type: GrantFiled: September 16, 2010Date of Patent: October 4, 2011Assignee: International Business Machines CorporationInventors: Dae-Gyu Park, Michael P. Chudzik, Vijay Narayanan, Vamsi Paruchuri
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Publication number: 20110121401Abstract: CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.Type: ApplicationFiled: February 2, 2011Publication date: May 26, 2011Applicant: International Business Machines CorporationInventors: Dae-Gyu Park, Michael P. Chudzik, Rashmi Jha, Siddarth A. Krishnan, Naim Moumen, Vijay Narayanan, Vamsi Paruchuri
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Patent number: 7947549Abstract: CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.Type: GrantFiled: February 26, 2008Date of Patent: May 24, 2011Assignee: International Business Machines CorporationInventors: Dae-Gyu Park, Michael P Chudzik, Rashmi Jha, Siddarth A Krishnan, Naim Moumen, Vijay Narayanan, Vamsi Paruchuri