Patents by Inventor Vamsi Paruchuri
Vamsi Paruchuri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7919379Abstract: The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.Type: GrantFiled: September 10, 2007Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Eduard A. Cartier, Rashmi Jha, Sivananda Kanakasabapathy, Xi Li, Renee T. Mo, Vijay Narayanan, Vamsi Paruchuri, Mark T. Robson, Kathryn T. Schonenberg, Michelle L. Steen, Richard Wise, Ying Zhang
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Patent number: 7880243Abstract: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators and metal containing gates. The metal layers of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. Due to the single common metal, device fabrication is simplified, requiring a reduced number of masks. Also, as a further consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted to each other in direct physical contact. Device thresholds are adjusted by the choice of the common metal material and oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.Type: GrantFiled: August 7, 2007Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Eduard Albert Cartier, Barry Paul Linder, Vijay Narayanan, Vamsi Paruchuri
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Publication number: 20110001195Abstract: A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.Type: ApplicationFiled: September 16, 2010Publication date: January 6, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dae-Gyu Park, Michael P. Chudzik, Vijay Narayanan, Vamsi Paruchuri
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Patent number: 7863126Abstract: A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.Type: GrantFiled: May 15, 2008Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Dae-Gyu Park, Michael P. Chudzik, Vijay Narayanan, Vamsi Paruchuri
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Patent number: 7847356Abstract: Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.Type: GrantFiled: August 18, 2009Date of Patent: December 7, 2010Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Bruce B. Doris, Vijay Narayanan, Vamsi Paruchuri
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Patent number: 7807525Abstract: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET device and in the PFET device. This identical portion contains at least a gate metal layer and a cap layer. Due to the identical portion, device fabrication is simplified, requiring a reduced number of masks. Furthermore, as a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted with each other in direct physical contact. Device thresholds are further adjusted by oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.Type: GrantFiled: August 10, 2009Date of Patent: October 5, 2010Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Eduard Albert Cartier, Barry Paul Linder, Vijay Narayanan, Vamsi Paruchuri
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Patent number: 7790592Abstract: Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.Type: GrantFiled: October 30, 2007Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Bruce B. Doris, Vijay Narayanan, Vamsi Paruchuri
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Patent number: 7785999Abstract: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.Type: GrantFiled: July 30, 2007Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Chester T. Dziobkowski, Sunfei Fang, Evgeni Gousev, Rajarao Jammy, Vijay Narayanan, Vamsi Paruchuri, Ghavam G. Shahidi, Michelle L. Steen, Clement H. Wann
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Patent number: 7723798Abstract: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET device and in the PFET device. This identical portion contains at least a gate metal layer and a cap layer. Due to the identical portion, device fabrication is simplified, requiring a reduced number of masks. Furthermore, as a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted with each other in direct physical contact. Device thresholds are further adjusted by oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.Type: GrantFiled: August 7, 2007Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Eduard Albert Cartier, Barry Paul Linder, Vijay Narayanan, Vamsi Paruchuri
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Publication number: 20090302396Abstract: Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.Type: ApplicationFiled: August 18, 2009Publication date: December 10, 2009Inventors: Tze-Chiang Chen, Bruce B. Doris, Vijay Narayanan, Vamsi Paruchuri
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Publication number: 20090291553Abstract: A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.Type: ApplicationFiled: August 4, 2009Publication date: November 26, 2009Applicant: International Business Machines CorporationInventors: Bruce B. Doris, Eduard Albert Cartier, Vijay Narayanan, Vamsi Paruchuri
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Publication number: 20090283838Abstract: A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.Type: ApplicationFiled: May 15, 2008Publication date: November 19, 2009Applicant: International Business Machines CorporationInventors: Dae-Gyu Park, Michael P. Chudzik, Vijay Narayanan, Vamsi Paruchuri
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Publication number: 20090212369Abstract: CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.Type: ApplicationFiled: February 26, 2008Publication date: August 27, 2009Applicant: International Business Machines CorporationInventors: Dae-Gyu Park, Michael P. Chudzik, Rashmi Jha, Siddarth A. Krishnan, Naim Moumen, Vijay Narayanan, Vamsi Paruchuri
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Publication number: 20090108366Abstract: Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Inventors: Tze-Chiang Chen, Bruce B. Doris, Vijay Narayanan, Vamsi Paruchuri
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Publication number: 20090065817Abstract: The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.Type: ApplicationFiled: September 10, 2007Publication date: March 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eduard A. Cartier, Rashmi Jha, Sivananda Kanakasabapathy, Xi Li, Renee T. Mo, Vijay Narayanan, Vamsi Paruchuri, Mark T. Robson, Kathryn T. Schonenberg, Michelle L. Steen, Richard Wise, Ying Zhang
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Publication number: 20090039434Abstract: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators and metal containing gates. The metal layers of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. Due to the single common metal, device fabrication is simplified, requiring a reduced number of masks. Also, as a further consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted to each other in direct physical contact. Device thresholds are adjusted by the choice of the common metal material and oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.Type: ApplicationFiled: August 7, 2007Publication date: February 12, 2009Inventors: Bruce B. Doris, Eduard Albert Cartier, Barry Paul Linder, Vijay Narayanan, Vamsi Paruchuri
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Publication number: 20090039435Abstract: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET device and in the PFET device. This identical portion contains at least a gate metal layer and a cap layer. Due to the identical portion, device fabrication is simplified, requiring a reduced number of masks. Furthermore, as a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted with each other in direct physical contact. Device thresholds are further adjusted by oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.Type: ApplicationFiled: August 7, 2007Publication date: February 12, 2009Inventors: Bruce B. Doris, Eduard Albert Cartier, Barry Paul Linder, Vijay Narayanan, Vamsi Paruchuri
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Publication number: 20090039436Abstract: A CMOS structure is disclosed in which both type of FET devices have gate insulators containing high-k dielectrics, and gates containing metals. The threshold of the two type of devices are adjusted in separate manners. One type of device has its threshold set by exposing the high-k dielectric to oxygen. During the oxygen exposure the other type of device is covered by a stressing dielectric layer, which layer also prevents oxygen penetration to its high-k gate dielectric. The high performance of the CMOS structure is further enhanced by adjusting the effective workfunctions of the gates to near band-edge values both NFET and PFET devices.Type: ApplicationFiled: August 7, 2007Publication date: February 12, 2009Inventors: Bruce B. Doris, Eduard Albert Cartier, Barry Paul Linder, Vijay Narayanan, Vamsi Paruchuri, Mark Todhunter Robson, Michelle L. Steen, Ying Zhang
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Publication number: 20080277726Abstract: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators and metal containing gates. The metal layers of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. As a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted to each other in direct physical contact. The FET device structures further contain stressed device channels, and gates with effective workfunctions of n+ Si and p+ Si values.Type: ApplicationFiled: May 8, 2007Publication date: November 13, 2008Inventors: Bruce B. Doris, Eduard Albert Cartier, Barry Paul Linder, Vijay Narayanan, Vamsi Paruchuri, Mark Todhunter Robson, Michelle L. Steen, Ying Zhang
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Publication number: 20080272437Abstract: A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.Type: ApplicationFiled: May 1, 2007Publication date: November 6, 2008Inventors: Bruce B. Doris, Eduard Albert Cartier, Vijay Narayanan, Vamsi Paruchuri