Patents by Inventor Vamsi Pavan Rayaprolu
Vamsi Pavan Rayaprolu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210042181Abstract: A memory access operation can be determined to have failed. A determination can be made as to whether a performance of a first error control operation has remedied the failure of the memory access operation. In response to determining that the first error control operation has remedied the failure of the memory access operation, an order of a performance of one or more prioritized error control operations of the plurality of prioritized error control operations can be changed for a subsequent memory access operation that has failed based on the first error control operation that has remedied the failure.Type: ApplicationFiled: August 6, 2019Publication date: February 11, 2021Inventors: Vamsi Pavan Rayaprolu, Harish R. Singidi, Kishore Kumar Muchherla, Ashutosh Malshe, Xiangang Luo
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Patent number: 10915395Abstract: Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight.Type: GrantFiled: November 16, 2018Date of Patent: February 9, 2021Assignee: Micron Technology, Inc.Inventors: Ting Luo, Kishore Kumar Muchherla, Harish Reddy Singidi, Xiangang Luo, Renato Padilla, Jr., Gary F. Besinga, Sampath Ratnam, Vamsi Pavan Rayaprolu
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Patent number: 10915400Abstract: One or more blocks from a pool of storage area blocks of the memory component are allocated to a first set of purposed blocks. First write operations are performed to write first data to first data stripes at user blocks of the memory component. Whether the blocks in the first set of purposed blocks satisfy a condition indicating that the first set of purposed blocks are to be retired is determined. Responsive to the blocks in the first set of purposed blocks satisfying the condition, one or more other blocks from the pool of storage area blocks of the memory component are allocated to a second set of purposed blocks. Second write operations are performed to write second data to second data stripes at the user blocks of the memory component.Type: GrantFiled: November 8, 2019Date of Patent: February 9, 2021Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Sampath K. Ratnam
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Publication number: 20210034274Abstract: A processing device in a memory system receives a first read request from a host system, wherein the first read request is directed to first data stored at a first address in a block of the memory component. The processing device determines that the first address is located within a first region of the block and increments a read counter for the block by a default amount. The processing device further receives a second read request from the host system, wherein the second read request is directed to second data stored at a second address in a block of the memory component, determines that the second address is located within a second region of the block and increments the read counter for the block by a scaled amount.Type: ApplicationFiled: August 2, 2019Publication date: February 4, 2021Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Harish R. Singidi, Gianni S. Alsasua
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Publication number: 20210035649Abstract: A processing device in a memory system determines that data stored in a first block of a plurality of blocks of a memory component satisfies a first threshold criterion pertaining to an age of the data. Responsive to the data stored in the first block satisfying the first threshold criterion, the processing device maintains a first counter to track a number of read operations performed on the first block. The processing device further determines that the data stored in the first block does not satisfy the first threshold criterion, and in response, maintains a second counter to track a number of read operations performed on a super block comprising the plurality of blocks.Type: ApplicationFiled: August 2, 2019Publication date: February 4, 2021Inventors: Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Ashutosh Malshe, Harish R. Singidi, Gianni S. Alsasua
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Publication number: 20210035642Abstract: A request to perform a write operation at a memory component can be received. A destination block of the memory component to store data of the write operation can be determined. A voltage pulse can be applied to the destination block that places a memory cell of the destination block at a voltage level associated with a high voltage state. Responsive to applying the voltage pulse to the destination block, an erase operation for the destination block can be performed to change the voltage level of the memory cell from the high voltage state to a low voltage state. A write operation can be performed to write the data to the destination block that is at the low voltage state.Type: ApplicationFiled: July 31, 2019Publication date: February 4, 2021Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe
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Publication number: 20200411083Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.Type: ApplicationFiled: September 10, 2020Publication date: December 31, 2020Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Kishore Kumar Muchherla, Sampath Ratnam, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Retano Padilla, JR.
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Patent number: 10871923Abstract: A program operation is executed on a memory sub-system. During execution of the program operation, a request to execute a read operation on the memory sub-system is received. In response to receiving the request, a program suspend operation to suspend the program operation is executed. The read operation is executed on the memory sub-system in response to a completion of the program suspend operation. In response to completion of the read operation, a program resume operation is executed. A program suspend delay period is established following execution of the program resume operation during which a subsequent read operation is stored in a queue.Type: GrantFiled: March 6, 2019Date of Patent: December 22, 2020Assignee: Micron Technology, Inc.Inventors: Jiangang Wu, Sampath K. Ratnam, Yang Zhang, Guang Chang Ye, Kishore Kumar Muchherla, Hong Lu, Karl D. Schuh, Vamsi Pavan Rayaprolu
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Patent number: 10872009Abstract: A number of operations that have been performed on one or more memory cells that are proximate to a particular memory cell of the memory component can be identified. A determination as to whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate can be made based on the identified number of operations. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.Type: GrantFiled: July 25, 2018Date of Patent: December 22, 2020Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy, Qisong Lin, Shane Nowell, Mustafa N. Kaynak
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Publication number: 20200371690Abstract: A system includes a memory component and a processing device to determine an amount of data stored at a region of a memory component and determine, based on the amount of data stored in the region of the memory component. The processing device determines a frequency to perform an operation on one or more memory cells of the region of the memory component. The processing device performs the operation on the one or more memory cells at the frequency to maintain the one or more memory cells of the region of the memory component in a first state associated with a first error rate for data stored at the one or more memory cells. The first error rate is less than a second error rate associated with a second state of the one or more memory cells.Type: ApplicationFiled: August 13, 2020Publication date: November 26, 2020Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Harish R. Singidi, Ashutosh Malshe, Kishore Kumar Muchherla
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Publication number: 20200348881Abstract: A processing device, operatively coupled with a memory device, is configured to identify a temperature related to a memory device of a plurality of memory devices; to determine, whether the temperature satisfies a threshold temperature condition; responsive to detecting that the temperature related to the memory device satisfies the threshold temperature condition, to identify an entry associated with the memory device from a plurality of entries in a data structure, wherein each entry of the plurality of entries corresponds to one of the plurality of memory devices; to determine a parameter value associated with the memory device from the entry, wherein the parameter value is for a programming operation to store data at the memory device; to adjust the parameter value associated with the memory device to generate an adjusted parameter value; and to store the adjusted parameter value in the entry of the data structure.Type: ApplicationFiled: July 15, 2020Publication date: November 5, 2020Inventors: Mustafa N Kaynak, Sampath K. Ratnam, Zixiang Loh, Nagendra Prasad Ganesh Rao, Larry K. Koudele, Vamsi Pavan Rayaprolu, Patrick R. Khayat, Shane Nowell
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Publication number: 20200319827Abstract: Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.Type: ApplicationFiled: June 23, 2020Publication date: October 8, 2020Inventors: Gianni Stephen Alsasua, Karl D. Schuh, Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Sampath Ratnam, Harish Reddy Singidi, Renato Padilla, JR.
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Patent number: 10796745Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.Type: GrantFiled: April 22, 2020Date of Patent: October 6, 2020Assignee: Micron Technology, Inc.Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Kishore Kumar Muchherla, Sampath Ratnam, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Renato Padilla, Jr.
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Publication number: 20200293203Abstract: A memory block of a non-volatile memory device is identified. The memory block has a first region and a second region, where a storage density of the first region is larger than the second region. Data is programmed at the first region of the memory block. An attribute of the memory block based on a sensor is received during programming of the data at the memory block. The attribute characterizes the data being programmed at the first region. The attribute is stored at a volatile during programming of the data at the memory block. The attribute is stored on a memory page of the second region responsive to the programming of the data at the first region being complete.Type: ApplicationFiled: June 1, 2020Publication date: September 17, 2020Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
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Publication number: 20200285416Abstract: A program operation is executed on a memory sub-system. During execution of the program operation, a request to execute a read operation on the memory sub-system is received. In response to receiving the request, a program suspend operation to suspend the program operation is executed. The read operation is executed on the memory sub-system in response to a completion of the program suspend operation. In response to completion of the read operation, a program resume operation is executed. A program suspend delay period is established following execution of the program resume operation during which a subsequent read operation is stored in a queue.Type: ApplicationFiled: March 6, 2019Publication date: September 10, 2020Inventors: Jiangang Wu, Sampath K. Ratnam, Yang Zhang, Guang Chang Ye, Kishore Kumar Muchherla, Hong Lu, Karl D. Schuh, Vamsi Pavan Rayaprolu
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Patent number: 10761727Abstract: A region of a memory component is determined to include a type of memory. A frequency to perform an operation on the region of the memory component is determined based on the type of memory. The operation is performed on a memory cell at the region of the memory component at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.Type: GrantFiled: November 19, 2018Date of Patent: September 1, 2020Assignee: MICRON TECHNOLOGY, INC.Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Harish R. Singidi, Ashutosh Malshe, Kishore Kumar Muchherla
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Patent number: 10747612Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.Type: GrantFiled: February 5, 2019Date of Patent: August 18, 2020Assignee: Micron Technology, Inc.Inventors: Harish Reddy Singidi, Kishore Kumar Muchherla, Xiangang Luo, Vamsi Pavan Rayaprolu, Ashutosh Malshe
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Publication number: 20200251162Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.Type: ApplicationFiled: April 22, 2020Publication date: August 6, 2020Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Kishore Kumar Muchherla, Sampath Ratnam, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Renato Padilla, JR.
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Patent number: 10732890Abstract: A temperature related to a memory device is identified. It is determined whether the temperature related to the memory device satisfies a threshold temperature condition. Responsive to detecting that the temperature related to the memory device satisfies the threshold temperature condition, a parameter for a programming operation is adjusted from a first value to a second value to store data at the memory device.Type: GrantFiled: March 6, 2018Date of Patent: August 4, 2020Assignee: MICRON TECHNOLOGY, INC.Inventors: Mustafa N. Kaynak, Sampath K. Ratnam, Zixiang Loh, Nagendra Prasad Ganesh Rao, Larry J. Koudele, Vamsi Pavan Rayaprolu, Patrick R. Khayat, Shane Nowell
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Patent number: 10719271Abstract: Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.Type: GrantFiled: November 16, 2018Date of Patent: July 21, 2020Assignee: Micron Technology, Inc.Inventors: Gianni Stephen Alsasua, Karl D. Schuh, Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Sampath Ratnam, Harish Reddy Singidi, Renato Padilla, Jr.