Patents by Inventor Vamsi Pavan Rayaprolu

Vamsi Pavan Rayaprolu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240370333
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising initiating a copyback operation to copy data from a first set of memory cells of the memory device to a second set of memory cells of the memory device; responsive to receiving a read command associated with a third set of memory cells configured to store a predefined number of bits per memory cell, suspending performing the copyback operation; performing a data integrity check on a subset of the third set of memory cells to obtain a data integrity metric value; responsive to determining that the data integrity metric value satisfies a threshold criterion, performing an error-handling operation on data stored on the third set of memory cells; and resuming performing the copyback operation.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Patrick R. Khayat, Vamsi Pavan Rayaprolu
  • Patent number: 12131795
    Abstract: A first analysis of each respective die of a multi-die memory device is performed. An equation to determine a respective temperature compensation (tempco) value for each respective die based on a number of program erase cycles (PECs) of the respective die based on the first analysis s determined. The equation for use in processing memory access requests directed to the respective die is stored. Whether to update the equation directed to the respective die based on a second analysis of the respective die is determined.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: October 29, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Steven Michael Kientz
  • Patent number: 12131790
    Abstract: A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: October 29, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Patent number: 12119068
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including detecting a power up event of the memory device, responsive to detecting the power up event, selecting an open block of the memory device, wherein the open block comprises a set of pages, determining, based at least in part on an analysis of the set of pages, whether the open block is valid for programming, and responsive to determining that the open block is valid for programming, keeping the open block open for programming.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: October 15, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Gary F. Besinga, Vamsi Pavan Rayaprolu, Steven Michael Kientz, Renato C. Padilla
  • Publication number: 20240329852
    Abstract: A processing device in a memory sub-system determines one or more read margin levels associated with the memory device. A machine learning model is applied to the one or more read margin levels to generate a read margin prediction value associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Inventors: Li-Te Chang, Murong Lang, Charles See Yeung Kwong, Vamsi Pavan Rayaprolu, Seungjune Jeon, Zhenming Zhou
  • Publication number: 20240302968
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device.
    Type: Application
    Filed: May 16, 2024
    Publication date: September 12, 2024
    Inventors: Jay Sarkar, Vamsi Pavan Rayaprolu, Ipsita Ghosh
  • Patent number: 12087369
    Abstract: A system can include a memory device and a processing device to perform operations that include detecting a transition associated with the memory device from a first power state to a second power state. Responsive to detecting the transition from the first power state to the second power state, the operations include determining a value of a scan frequency in view of the second power state, wherein one or more scan iterations are initiated in accordance with the value of the scan frequency. The operations further include performing one or more block family calibration operations in accordance with the value of the scan frequency.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: September 10, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Vamsi Pavan Rayaprolu
  • Publication number: 20240296092
    Abstract: A request to access data programmed to a memory sub-system is received. A determination is made of whether a memory device that stores the data referenced by the request satisfies a weak memory device criterion in view of a quality rating for the device. In response to a determination that the memory device satisfies the weak memory device criterion, an error correction operation to access the data is performed in accordance with the request.
    Type: Application
    Filed: May 3, 2024
    Publication date: September 5, 2024
    Inventors: Vamsi Pavan Rayaprolu, Dung Viet Nguyen, Zixiang Loh, Sampath K. Ratnam, Patrick R. Khayat, Thomas Herbert Lentz
  • Publication number: 20240289032
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order; and determining an optimized order of the set of error-handling operations based on probability data and latency data, wherein the probability data is associated with a result of running the sample data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.
    Type: Application
    Filed: May 9, 2024
    Publication date: August 29, 2024
    Inventors: Aswin Thiruvengadam, Vamsi Pavan Rayaprolu
  • Patent number: 12072762
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; responsive to determining that a data integrity metric value satisfies the threshold criterion, performing a first error-handling operation on the data stored on the source set of memory cells; responsive to determining that the first error-handling operation fails to correct the data, performing a second error-handling operation on the data; and responsive to determining that the second error-handling operation corrected the data, causing the memory device to copy the corrected data to a destination set of memory cells of the memory device.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: August 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Patrick R. Khayat, Vamsi Pavan Rayaprolu
  • Publication number: 20240257887
    Abstract: A configuration setting manager of a memory device receives a request to perform an adjustment operation on one or more configuration setting values of the memory device; calculate one or more updated configuration setting values by applying a multiplier value to the one or more configuration setting values based on a configuration adjustment definition associated with the one or more configuration setting values, wherein the multiplier value is associated with a number of memory operations performed on the memory device; and store the one or more updated configuration setting values to one or more corresponding configuration registers.
    Type: Application
    Filed: April 9, 2024
    Publication date: August 1, 2024
    Inventors: Tawalin Opastrakoon, Renato C. Padilla, Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Michael G. Miller, Gary F. Besinga, Christopher M. Smitchger
  • Publication number: 20240256145
    Abstract: A memory system includes a memory device and a processing device, operatively coupled to the memory device. The processing device performs operations comprising: identifying one or more mandatory scan wordlines of the memory device and one or more remaining wordlines of the memory device; performing a plurality of scan iterations with respect to a plurality of pages of the memory device, such that performing each scan iteration comprises: identifying, among the remaining wordlines, one or more scheduled scan wordlines of the memory device, scanning a subset of pages of the memory device that are addressable by the mandatory scan wordlines and the scheduled scan wordlines; wherein a combination of a first plurality of pages addressable by the scheduled scan wordlines selected by the plurality of scan iterations and a second plurality of pages addressable by the mandatory wordlines comprises the plurality of pages of the memory device.
    Type: Application
    Filed: April 12, 2024
    Publication date: August 1, 2024
    Inventors: Vamsi Pavan Rayaprolu, Christopher M. Smitchger, Saeed Sharifi Tehrani
  • Publication number: 20240256375
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including selecting sample data residing in the memory device; running a test on the sample data regarding a set of error-handling operations; and generating log data comprising a first order of the set of error-handling operations to be performed on data residing in a segment of the memory device.
    Type: Application
    Filed: April 10, 2024
    Publication date: August 1, 2024
    Inventors: Jay Sarkar, Ipsita Ghosh, Vamsi Pavan Rayaprolu
  • Patent number: 12050777
    Abstract: A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, one or more read margin levels corresponding to a page type associated with the memory device are determined. A machine learning model is applied to the one or more read margin levels to generate a margin prediction value based on the page type and a wordline group associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.
    Type: Grant
    Filed: August 3, 2022
    Date of Patent: July 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Li-Te Chang, Murong Lang, Charles See Yeung Kwong, Vamsi Pavan Rayaprolu, Seungjune Jeon, Zhenming Zhou
  • Publication number: 20240241672
    Abstract: One or more trim values associated with a set of blocks of a memory device are set according to a representative number of program erase cycles (PECs) for the set of blocks. Each block in the set of blocks was programmed within at least one of a specified time window or a specified temperature range. Responsive to executing a program operation on a block of the set of blocks according to the one or more trim values, an indicator is set to reflect the one or more trim values used during the execution of the program operation. Responsive to receiving a request to perform a read operation directed to the block of the set of blocks, a read offset value corresponding to the indicator is determined. The read operation is performed using the read offset value.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Inventors: Steven Michael Kientz, Ugo Russo, Vamsi Pavan Rayaprolu
  • Patent number: 12040025
    Abstract: A system includes a memory device including an block and a processing device, operatively coupled with the memory device, to perform operations including initiating a page scan with respect to a page of the block, determining whether to perform an erased page check, and in response to determining that the erased page check is not to be performed, performing a two-sided page scan with calibration feedback.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: July 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Patrick R. Khayat, Hyung Seok Kim, Steven Michael Kientz
  • Patent number: 12032833
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order associated with a workload; obtaining error recovery data as a result of running the sample data; and determining an optimized order of the set of error-handling operations based on probability of error recovery and latency data, wherein the probability of error recovery is based on the error recovery data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: July 9, 2024
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Aswin Thiruvengadam, Vamsi Pavan Rayaprolu
  • Patent number: 12019874
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including applying an ordered set of error-handling operations to be performed on data residing in a segment of the memory device as an input to a trained machine learning model, wherein the trained machine learning model is based on latency data for previously-performed error-handling operations; and obtaining an output of the trained machine learning model, the output comprising a reordered set of error-handling operations to be performed on the data residing in the segment of the memory device, and wherein the reordered set adjusts an order of one or more error-handling operations of the ordered set of error-handling operations.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: June 25, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jay Sarkar, Vamsi Pavan Rayaprolu, Ipsita Ghosh
  • Patent number: 12007838
    Abstract: A request to access data programmed to a memory sub-system is received. A determination is made of whether memory cells of the memory sub-system that store the programmed data satisfy one or more cell degradation criteria. In response to a determination that the memory cells satisfy the one or more cell degradation criteria, an error correction operation to access the data is performed in accordance with the request.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: June 11, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Dung Viet Nguyen, Zixiang Loh, Sampath K Ratnam, Patrick R. Khayat, Thomas Herbert Lentz
  • Patent number: 12009042
    Abstract: A trigger rate associated with a scan operation of a set of memory pages of a data block is identified. The trigger rate is compared to a threshold rate to determine that a condition is satisfied. In response to satisfying the condition, a refresh operation is executed on the set of memory pages of the data block.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: June 11, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Ashutosh Malshe, Gianni S. Alsasua, Harish R. Singidi