Patents by Inventor Vamsi Pavan Rayaprolu

Vamsi Pavan Rayaprolu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11636908
    Abstract: A memory device to calibrate voltages used to read a group of memory cells. For example, the memory device measures first signal and noise characteristics of a group of memory cells by reading the group of memory cells at first test voltages that are separated from each other by a first voltage interval. An estimate of a read level of the group of memory cells is determined based on the first signal and noise characteristics. The memory device then measures second signal and noise characteristics of the group of memory cells by reading the group of memory cells at second test voltages that are separated from each other by a second voltage interval that is smaller than the first voltage interval. An optimized read voltage for the read level is computed from the second signal and noise characteristics.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: April 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Walter Di Francesco, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Jeffrey Scott McNeil, Jr.
  • Publication number: 20230110545
    Abstract: A request to perform a secure erase operation for a memory component can be received. A voltage level of a pass voltage that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied during a program operation to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can exceed the pass voltage applied to the unselected wordlines of the memory component during the read operation.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 13, 2023
    Inventors: Kishore Kumar Muchherla, Harish R. Singidi, Vamsi Pavan Rayaprolu, Ashutosh Malshe, Sampath K. Ratnam
  • Patent number: 11625177
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: April 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shane Nowell, Michael Sheperek, Larry J. Koudele, Vamsi Pavan Rayaprolu
  • Publication number: 20230097679
    Abstract: Technologies for performing a quick reliability scan include, for a particular block of a set of blocks of different block types, each block of the set of blocks including pages of memory of a physical memory device, identifying subset of the pages of the block. The block is scanned by scanning the subset of the plurality of pages of the block for a fold condition. A page of the subset of the plurality of pages is determined to have the fold condition. After the set of blocks has been scanned, the folding of the block that includes the page that has been determined to have the fold condition is requested.
    Type: Application
    Filed: December 6, 2022
    Publication date: March 30, 2023
    Inventors: Saeed Sharifi Tehrani, Vamsi Pavan Rayaprolu
  • Patent number: 11615858
    Abstract: A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: March 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Publication number: 20230085178
    Abstract: A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.
    Type: Application
    Filed: November 22, 2022
    Publication date: March 16, 2023
    Inventors: Vamsi Pavan Rayaprolu, Karl D. Schuh, Jeffrey S. McNeil Jr., Kishore K. Muchherla, Ashutosh Malshe, Jiangang Wu
  • Patent number: 11604601
    Abstract: A memory sub-system to, in response to a power up, initiate a first loading process associated with a set of trim values, wherein the first loading process includes loading a sequence of the set of trim values to one or more registers of the memory sub-system. An operation associated with a memory unit of the memory sub-system is identified. A portion of the set of trim values corresponding to the operation associated with the memory unit is identified. The memory sub-system executes a second loading process comprising loading the portion of the set of trim values corresponding to the operation associated with the memory unit. The operation is executed using the portion of the set of trim values loaded into the one or more registers associated with the memory unit.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: March 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Steven Michael Kientz, Vamsi Pavan Rayaprolu
  • Publication number: 20230076362
    Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.
    Type: Application
    Filed: November 10, 2022
    Publication date: March 9, 2023
    Inventors: Michael G. Miller, Ashutosh Malshe, Gianni Stephen Alsasua, Renato Padilla, JR., Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Harish Reddy Singidi
  • Patent number: 11599286
    Abstract: A method includes determining respective valid translation unit counts of a block of non-volatile memory cells over a period of time, determining a rate of change of the respective valid translation unit counts of the block of non-volatile memory cells over the period of time, comparing the rate of change of the valid translation unit counts to a bin transition rate, and based on comparing the rate of change of the valid translation unit counts to the bin transition rate, performing a media management operation on the block of non-volatile memory cells.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Publication number: 20230057863
    Abstract: A method includes determining that a ratio of valid data portions of a block of memory cells is greater than or less than a valid data portion threshold and performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions is greater than the valid data portion threshold. The method further includes performing a second media management operation on the block of memory cells in response to determining that the ratio of valid data portions is less than the valid data portion threshold.
    Type: Application
    Filed: November 7, 2022
    Publication date: February 23, 2023
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Publication number: 20230059923
    Abstract: A trigger rate associated with a scan operation of a set of memory pages of a data block is identified. The trigger rate is compared to a threshold rate to determine that a condition is satisfied. In response to satisfying the condition, a refresh operation is executed on the set of memory pages of the data block.
    Type: Application
    Filed: November 3, 2022
    Publication date: February 23, 2023
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Ashutosh Malshe, Gianni S. Alsasua, Harish R. Singidi
  • Publication number: 20230049877
    Abstract: A first host data item and a second host data item are received. The first host data item is stored in a first page of a first logical unit of a memory device, where the first page is one of a plurality of pages associated with redundancy metadata. A second page a second page of a second logical unit of the memory device is identified, where the second page is one of the plurality of pages associated with the redundancy metadata, and the first page and the second page are associated with different wordlines of the memory device. The second host data item is stored in the second page of the second logical unit of the memory device. The first page and the second page can be associated with a fault tolerant stripe that includes the redundancy metadata.
    Type: Application
    Filed: October 31, 2022
    Publication date: February 16, 2023
    Inventors: Tawalin Opastrakoon, Renato C. Padilla, Michael G. Miller, Christopher M. Smitchger, Gary F. Besinga, Sampath K. Ratnam, Vamsi Pavan Rayaprolu
  • Patent number: 11567665
    Abstract: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Patent number: 11561722
    Abstract: A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device, to store host data in the page of the data unit. The processing device further generates a parity page for the host data stored in the page of the data unit and adds the parity page to parity data stored at a parity data storage location. Responsive to determining that a first size of the stored parity data satisfies a first condition, the processing device initiates execution of a compression algorithm to compress the stored parity data. Responsive to determining that a second size of the parity data resulting from the execution of the compression algorithm satisfies a second condition, the processing device performs a scan operation to release at least a subset of the stored parity data.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Harish R Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla
  • Publication number: 20230012978
    Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write a plurality of flag bits within a group of memory cells programmed by the multi-pass programming command. The system also includes a processing device, operatively coupled to the memory component. The processing device is to detect an error in attempting to read a top page of the group of memory cells, determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error due to the top page of the group of memory cells being incompletely programmed.
    Type: Application
    Filed: September 16, 2022
    Publication date: January 19, 2023
    Inventors: Qisong LIN, Vamsi Pavan RAYAPROLU, Jiangang WU, Sampath K. RATNAM, Sivagnanam PARTHASARATHY, Shao Chun SHI
  • Patent number: 11557357
    Abstract: An example memory sub-system to receive a request to execute a read operation associated with data of a memory unit of a memory sub-system. A time after program associated with the data is determined. The time after program is compared to a threshold time level to determine if a first condition is satisfied or a second condition is satisfied. The memory sub-system selects one of a first set of read offset values based on the time after program in response to satisfying the first condition, or a second set of read offset values based on a data state metric measurement in response to satisfying the second condition.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Larry J. Koudele
  • Patent number: 11545232
    Abstract: Technologies for performing a quick reliability scan include, for a particular block of a set of blocks of different block types. Each block of the set of blocks includes pages of memory of a physical memory device. A subset of the pages of the block is identified. The block is scanned by scanning the subset of the plurality of pages of the block for a fold condition. A page of the subset of the plurality of pages is determined to have the fold condition. After the set of blocks has been scanned, the folding of the block that includes the page that has been determined to have the fold condition is requested.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: January 3, 2023
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Saeed Sharifi Tehrani, Vamsi Pavan Rayaprolu
  • Patent number: 11544008
    Abstract: A memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: January 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Gianni Stephen Alsasua, Karl D. Schuh, Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Sampath Ratnam, Harish Reddy Singidi, Renato Padilla, Jr.
  • Publication number: 20220415412
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric associated with data stored in a part of a block of the memory device; responsive to determining that the value of the data state metric satisfies a first threshold criterion, determining a first value reflecting a voltage distribution metric associated with at least the part of the block; determining a second value reflecting at least one of a deterioration slope indicative of a data deterioration rate associated with a first portion of the memory device or an error rate associated with a second portion of the memory device; feeding the first value and the second value to a neural network; and receiving, from the neural network, an instruction to perform a media management operation.
    Type: Application
    Filed: September 7, 2022
    Publication date: December 29, 2022
    Inventors: Vamsi Pavan Rayaprolu, Christopher M. Smitchger
  • Patent number: 11527291
    Abstract: A request to perform a secure erase operation for a memory component can be received. A voltage level that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can be associated with a program operation to place a memory cell of the memory component at another voltage level that exceeds the voltage level that is applied to the unselected wordlines of the memory component during the read operation.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: December 13, 2022
    Assignee: MICRON TECHNOLOGY, INC
    Inventors: Kishore Kumar Muchherla, Harish R. Singidi, Vamsi Pavan Rayaprolu, Ashutosh Malshe, Sampath K. Ratnam