Abstract: A telecommunications system and method is provided, having a network services processor (NSP) for handling telecommunications in conformance with a predefined signaling system and for distributing processing tasks including call handling and routing to a plurality of resources, comprising: a plurality of packet managers (PMs) for accessing, processing, and distributing packetized call data over a packet network; a plurality of media control platforms (MCPs) for accessing, processing, and distributing application tasks (MCTs) transmitted from the NSP; and a plurality of interconnect controllers (ICCs), each for interfacing the NSP with the plurality of resources including the PMs and the MCPs, wherein the processing tasks are handled by the plurality of resources by concurrent and decentralized processing, and the ICC includes a centralized maintenance platform (CMP) for monitoring the plurality of resources via centralized messaging and for determining resource failures by processing responses to the centrali

Abstract: A software-based telecommunications switch architecture with distributed supervision, network communications, and signal processing provides an expandable call volume handling capacity without having to add additional supervisory processing capability. The call signals are processed by a plurality of media control platforms which communicate with a supervisory network services processor and communicate with the network through a packet manager. The switch can be expanded by adding more media control platforms without the need to provide a new or additional network services processor or packet manager.

Abstract: A method of call processing includes passing, over a local area network, control signals from a centralized controller to each of a plurality of decentralized processors. The method also includes having each of the plurality of decentralized processors, in response to the control signals, executing decentralized call control functions.

Abstract: A software adaptation of a Time Division Multiplexing (TDM) telecommunications line and trunk group control sub-system is described. The adaptation permits this legacy software to run under various operating systems and provide essential functions to a packet based switching system. This method of reuse permits continual use of proven and dependable software features to operate under new packet based topologies. The legacy software runs in a new soft-switch environment with minimal redesign. Timer and interrupt functions are altered to comply with off-the-shelf operating systems. Error recovery and restart operations are isolated to remove awareness from the operating system but still permit the legacy software to recover in conventional manner.

Abstract: A dovetail joint between a rotor wheel and a bucket includes a male dovetail component on the rotor wheel and a female dovetail component in the bucket. The male dovetail component has axially projecting hooks with slanted crush surfaces along generally radially inwardly directed surfaces. The slanted surfaces form included angles with neck portions parallel to a plane normal to the axis of rotation which are larger than 90.degree. and decrease in included angle from the radially outermost hooks to the radially innermost hook where the angle is 90.degree.. Compound fillets are also provided along the transition surfaces between the slanted crush surfaces and the neck surfaces. Thus, stress concentrations are minimized.

Abstract: In a data processing system, a memory control unit (22) provides a control register bit field (60), logic, and a state machine (62) which facilitate a programmable number of clocks for an initial access to an on-chip memory (20). Specifically, the memory control unit (22) allows an external user to modify memory control signals to provide consistent access times across different frequencies of the system clock and allows memory control signals to be modified to optimize access time dynamically. Also, programmable control of the control signals to the memory (20) allows the memory to operate at system clock frequencies which are higher than expected.

Abstract: Clock frequency and number of stages of a charge pump for nonvolatile memories are automatically adjusted to compensate for lower efficiency due to lower power supply, higher temperature, or weaker process. A low voltage detector will cause the charge pump to increase the charge pump's clock frequency and number of stages when a low voltage is detected, making the charge pump's capability constant over a voltage range. A counter timing programming/erasing time will cause the charge pump clock frequency and number of stages to increase when the programming/erasing time exceeds certain thresholds. This boosts the charge pump's drivability for a weaker process, higher temperature, or aged cells.