Abstract: A (pre) driver circuit includes first and second output terminals configured to be coupled to a power transistor. A differential stage has non-inverting and inverting inputs for receiving an input voltage. The input voltage is replicated as an output voltage across the first and second output terminals as a drive signal for the power transistor. The differential stage includes a differential transconductance amplifier in a voltage follower arrangement configured to provide continuous regulation of a voltage at the first output terminal with respect to the second output terminal.

Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.

Abstract: A ringing peak detector circuit includes an input buffer receives a pair of differential feedback signals indicating a drain-source voltage of the at least one low side electronic switch. The input buffer generates shifted differential feedback signals having a common mode voltage that is equal to approximately one half of the supply voltage. A peak detector circuit is coupled to the input buffer to receive the shifted differential voltage signals. The peak detector circuit detects a peak value of an oscillation on the inductive electric load and to generate an output signal indicating the detected peak value. A circuit generates a control signal based on the detected peak value and a maximum value, with the control signal being applied to the inductive electrical load driver to control switching of the at least one low side switch.

Abstract: A circuit includes a switching circuit including a first switch and a second switch. A current sensing circuit is coupled to the switching circuit to sense a first current through the first switch and to generate a first sensed current signal based on the sensed first current, and configured to sense a second current through the second switch and to generate a second sensed current signal based on the sensed second current. An output circuit is coupled to the current sensing circuit and is configured to generate a failure signal based on the first sensed current signal and the second sensed current signal.

Abstract: A circuit includes a differential stage configured to provide a differential output signal. An analog-to-digital converter is coupled to first and second output nodes of the differential stage. The analog-to-digital converter is configured to provide an output signal that is a function of the differential output signal from the differential stage. A multiplexer is configured to receive a differential input signal. The multiplexer includes a test switch switchable between a conductive state and a non-conductive state. In the conductive state, the test switch couples the first input node and the second input node of the differential stage. Test signal injection circuitry is activatable to force a differential current through the differential stage. The circuit is selectively switchable between an operational mode and a self-test mode.

Abstract: A method of operating a control device includes performing an open load test or a current leakage test. The open load test includes activating a first current and then a second current and sensing with the first and the second current activated, respectively, first and second voltage drops between charge distribution pins and charge sensing pins of the control device. Respective differences are calculated between the first and second voltage drops sensed with the first current and second current activated, respectively. These differences are compared with respective thresholds and an open circuit condition is declared as a result of the differences calculated reaching these thresholds.

Abstract: A device to read a variable resistor has an analog to digital converter (ADC), a first switch and a second switch. The ADC has a first ADC input, a second ADC input and an ADC output. The first switch selectively couples a first voltage indicative of a voltage across a first resistance to the first ADC input. The second switch selectively couples a second voltage indicative of a voltage across a second resistance to the second ADC input. The ADC outputs a signal indicative of a value of the second resistance.

Abstract: A device measures the current in an inductive load using two separate current-measuring paths to detect the current in the inductive load. The inductive load is connected between first and second nodes, and the first node connected to a first voltage. The device includes first and second transistors cascaded together between the first node and a third node that is connected to a second voltage. First and second sense amplifiers measure the current in the inductive load. The first and second sense amplifiers are connected to at least one terminal of the first and second transistors. Two blocks sample and hold signals from the first and second sense amplifiers, which represent, respectively, the currents in the two separate current-measuring paths. The two currents are subtracted in a comparison node for generating an error signal that is compared with a predefined window and if outside the window a failure signal is generated.

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

Abstract: A device to read a variable resistor has an analog to digital converter (ADC), a first switch and a second switch. The ADC has a first ADC input, a second ADC input and an ADC output. The first switch selectively couples a first voltage indicative of a voltage across a first resistance to the first ADC input. The second switch selectively couples a second voltage indicative of a voltage across a second resistance to the second ADC input. The ADC outputs a signal indicative of a value of the second resistance.

Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

Abstract: A device measures the current in an inductive load using two separate current-measuring paths to detect the current in the inductive load. The inductive load is connected between first and second nodes, and the first node connected to a first voltage. The device includes first and second transistors cascaded together between the first node and a third node that is connected to a second voltage. First and second sense amplifiers measure the current in the inductive load. The first and second sense amplifiers are connected to at least one terminal of the first and second transistors. Two blocks sample and hold signals from the first and second sense amplifiers, which represent, respectively, the currents in the two separate current-measuring paths. The two currents are subtracted in a comparison node for generating an error signal that is compared with a predefined window and if outside the window a failure signal is generated.

Abstract: A device measures the current in an inductive load using two separate current-measuring paths to detect the current in the inductive load. The inductive load is connected between first and second nodes, and the first node connected to a first voltage. The device includes first and second transistors cascaded together between the first node and a third node that is connected to a second voltage. First and second sense amplifiers measure the current in the inductive load. The first and second sense amplifiers are connected to at least one terminal of the first and second transistors. Two blocks sample and hold signals from the first and second sense amplifiers, which represent, respectively, the currents in the two separate current-measuring paths. The two currents are subtracted in a comparison node for generating an error signal that is compared with a predefined window and if outside the window a failure signal is generated.

Abstract: A ringing peak detector circuit includes an input buffer receives a pair of differential feedback signals indicating a drain-source voltage of the at least one low side electronic switch. The input buffer generates shifted differential feedback signals having a common mode voltage that is equal to approximately one half of the supply voltage. A peak detector circuit is coupled to the input buffer to receive the shifted differential voltage signals. The peak detector circuit detects a peak value of an oscillation on the inductive electric load and to generate an output signal indicating the detected peak value. A circuit generates a control signal based on the detected peak value and a maximum value, with the control signal being applied to the inductive electrical load driver to control switching of the at least one low side switch.

Abstract: A ringing peak detector module detects a ringing at the output of an inductive load driver including a bridge circuit containing high side and low side switches. A ringing peak detector receives differential feedback signals representative of the drain-source voltage of the low-side switch and detects a ringing peak of an oscillation of a current/voltage on the inductive load. A module compares said detected ringing peak with a maximum value and controls said driver by an error signal calculated as a function of the difference between said peak value and maximum value. The ringing peak detector module includes an input buffer module upstream of said peak detector circuit that shifts the differential feedback signals so a common mode of these signals is centered at a half-dynamic level of a supply voltage to provide correspondingly shifted voltages forming a shifted differential output corresponding to a steady state of the differential feedback signals.

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

Abstract: A ringing peak detector module detects a ringing at the output of an inductive load driver including a bridge circuit containing high side and low side switches. A ringing peak detector receives differential feedback signals representative of the drain-source voltage of the low-side switch and detects a ringing peak of an oscillation of a current/voltage on the inductive load. A module compares said detected ringing peak with a maximum value and controls said driver by an error signal calculated as a function of the difference between said peak value and maximum value. The ringing peak detector module includes an input buffer module upstream of said peak detector circuit that shifts the differential feedback signals so a common mode of these signals is centered at a half-dynamic level of a supply voltage to provide correspondingly shifted voltages forming a shifted differential output corresponding to a steady state of the differential feedback signals.

Abstract: A (pre) driver circuit includes first and second output terminals configured to be coupled to a power transistor. A differential stage has non-inverting and inverting inputs for receiving an input voltage. The input voltage is replicated as an output voltage across the first and second output terminals as a drive signal for the power transistor. The differential stage includes a differential transconductance amplifier in a voltage follower arrangement configured to provide continuous regulation of a voltage at the first output terminal with respect to the second output terminal.

Abstract: A fail-safe device may be coupled to a main device for actuating a switch responsive to a failure. The fail-safe device may include a fail-safe circuit, and an isolation trench surrounding the fail-safe circuit and isolating the fail-safe circuit from the main device. The fail-safe device may include an internal power supply connection, an internal reference voltage connection, a self-biased drive block configured to drive the at least one switch, and a receiver configured to receive failure signals from the main device.