Abstract: Transistor characteristics may be adjusted on the basis of asymmetrically formed cavities in the drain and source areas so as to maintain a strain-inducing mechanism while at the same time providing the possibility of obtaining asymmetric configuration of the drain and source areas while avoiding highly complex implantation processes. For this purpose, the removal rate during a corresponding cavity etch process may be asymmetrically modified on the basis of a tilted ion implantation process.

Abstract: By incorporating a diffusion hindering species at the vicinity of PN junctions of P-channel transistors comprising a silicon/germanium alloy, diffusion related non-uniformities of the PN junctions may be reduced, thereby contributing to enhanced device stability and increased overall transistor performance. The diffusion hindering species may be provided in the form of carbon, nitrogen and the like.

Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.

Abstract: By providing a substantially non-damaged semiconductor region between a pre-amorphization region and the gate electrode structure, an increase of series resistance at the drain side during the re-crystallization may be reduced, thereby contributing to overall transistor performance, in particular in the linear operating mode. Thus, symmetric and asymmetric transistor architectures may be achieved with enhanced performance without unduly adding to overall process complexity.

Abstract: An integrated circuit device includes a degradable test structure, a first external interface pin and a second external interface pin, a first conductive path coupling a first node of the degradable test structure and the first external interface pin, and a second conductive path coupling a second node of the degradable test structure and the second external interface pin. Another integrated circuit device includes a non-volatile memory device, a counter comprising an input configured to receive a first clock signal and an output to provide a count value, and control logic configured to store the count value of the counter in the non-volatile memory, whereby the non-volatile memory is externally accessible.

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract: An integrated circuit device includes a degradable test structure, a first external interface pin and a second external interface pin, a first conductive path coupling a first node of the degradable test structure and the first external interface pin, and a second conductive path coupling a second node of the degradable test structure and the second external interface pin. Another integrated circuit device includes a non-volatile memory device, a counter comprising an input configured to receive a first clock signal and an output to provide a count value, and control logic configured to store the count value of the counter in the non-volatile memory, whereby the non-volatile memory is externally accessible.

Abstract: A test system configured to detect discontinuities in packaged devices. A test unit includes a pulse generator and a sampling circuit. The packaged device is coupled to the test unit via a test fixture. The test unit is configured to transmit a pulse to the packaged device through the test fixture, receive a reflected signal from the packaged device through the test fixture in response to the transmitted pulse, and analyze the reflected signal to detect a discontinuity within the packaged device and/or determine the location of a discontinuity within the packaged device. The test system is configured to store a calibration dataset which includes a set of sample values corresponding to a time domain reflectometry (TDR) test of a calibration packaged device. The test unit is configured to compare data corresponding to the reflected signal to stored values of the calibration dataset to detect a discontinuity in the packaged device.