Patents by Inventor Vasudevan Parthasarathy
Vasudevan Parthasarathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160182156Abstract: A system includes an adjustable receiver a data line, a communications bus, and signal processing circuitry. The adjustable receiver may receive a signal and pass the received signal to the signal processing circuitry for data recovery and processing. For example, the adjustable receiver may detect an optical signal and pass the detected signal to signal processing circuitry for analog-to-digital conversion and digital processing. The signal processing circuitry may apply criteria to received signal to determine adjustment of selected parameters for the adjustable receiver. The signal processing circuitry may access addressable parameters in the adjustable receiver via the communications bus. By addressing the parameters the signal processing circuitry may apply the determined adjustments to the selected parameters in the adjustable receiver.Type: ApplicationFiled: January 31, 2015Publication date: June 23, 2016Inventors: Frederick Sugihwo Tang, Vasudevan Parthasarathy, John Szeming Wang, Rajiv Pancholy
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Patent number: 9270291Abstract: Methods and apparatuses are described for timing skew mitigation in time-interleaved ADCs (TI-ADCs) that may be performed for any receive signal without any special signals during blind initialization, which may be followed by background calibration. The same gain/skew calibration metrics may be applied to baud sampled and oversampled systems, including wideband receivers and regardless of any modulation, by applying a timing or frequency offset to non-stationary sampled signals during initial training. Skew mitigation is low latency, low power, low area, noise tolerant and scalable. Digital estimation may be implemented with accumulators and multipliers while analog calibration may be implemented with adjustable delays. DC and gain offsets may be calibrated before skew calibration. The slope of the correlation function between adjacent samples may be used to move a timing skew estimate stochastically at a low adaptive rate until the skew algorithm converges.Type: GrantFiled: March 18, 2015Date of Patent: February 23, 2016Assignee: Broadcom CorporationInventors: Gavin D. Parnaby, Vasudevan Parthasarathy, John S. Wang
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Publication number: 20150207502Abstract: Reference-less repeating circuits provide significant advantages over repeating circuits requiring external frequency references. These repeating circuits eliminate the need for external frequency references provide significant power, layout, and physical isolation advantages. Digitally controlled reference-less repeating circuits have a relatively narrow frequency detection range, but typically consume significantly less power than analog repeating circuits while providing data rate flexibility, particularly at lower data rates. Due to the narrow frequency detection range of digitally controlled reference-less repeating circuits, efficient frequency estimation techniques allow these circuits to quickly lock to an input signal, and provide an accurate repeated output signal.Type: ApplicationFiled: April 7, 2014Publication date: July 23, 2015Applicant: BROADCOM CORPORATIONInventors: MAGESH VALLIAPPAN, AFSHIN MOMTAZ, NAMIK KOCAMAN, VASUDEVAN PARTHASARATHY
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Patent number: 9077328Abstract: Reference-less repeating circuits provide significant advantages over repeating circuits requiring external frequency references. These repeating circuits eliminate the need for external frequency references provide significant power, layout, and physical isolation advantages. Digitally controlled reference-less repeating circuits have a relatively narrow frequency detection range, but typically consume significantly less power than analog repeating circuits while providing data rate flexibility, particularly at lower data rates. Due to the narrow frequency detection range of digitally controlled reference-less repeating circuits, efficient frequency estimation techniques allow these circuits to quickly lock to an input signal, and provide an accurate repeated output signal.Type: GrantFiled: April 7, 2014Date of Patent: July 7, 2015Assignee: Broadcom CorporationInventors: Magesh Valliappan, Afshin Momtaz, Namik Kocaman, Vasudevan Parthasarathy
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Patent number: 9041571Abstract: Systems and methods are provided for calibrating an analog to digital converter (ADC) using one or more feedback mechanisms. In an embodiment, a capture memory module captures a portion of ADC data and post-processes the captured data using a microprocessor to perform calibration. Using the microprocessor, the capture memory module calibrates the ADC until the output of the ADC is within a desired range. In an embodiment, the capture memory module also captures a portion of data output from a digital correction module and post-processes this captured data using the microprocessor. Using the microprocessor, the capture memory module calibrates the digital correction module until the output of the digital correction module is within a desired range.Type: GrantFiled: September 6, 2013Date of Patent: May 26, 2015Assignee: Broadcom CorporationInventors: John Wang, Vasudevan Parthasarathy
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Patent number: 9031178Abstract: Systems that allow for DFE functionality to be eliminated from the receiver side of a communication system and for a DFE-like functionality to be implemented instead at the transmitter side of the communication system are provided. By removing the DFE functionality from the receiver side, error propagation can be eliminated at the receiver and receiver complexity can be reduced drastically. At the transmitter side, the DFE-like functionality provides the same DFE benefits, and with the transmitter environment being noise-free, no errors can occur due noise boosting, for example. The DFE-like functionality at the transmitter side can be implemented using non-linear (recursive or feed-forward) pre-coders or a combination of non-linear pre-coders and linear filters, which can be configured to invert a net communication channel between the transmitter and the receiver. Embodiments particularly suitable for fiber optic channels and server backplane channels are also provided.Type: GrantFiled: September 30, 2013Date of Patent: May 12, 2015Assignee: BroadcomInventors: William Bliss, Vasudevan Parthasarathy
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Patent number: 9025693Abstract: Systems and methods that facilitate on-chip testing are provided. An integrated circuit can include a transmitter configured to transmit a communications signal via a communications channel. The integrated circuit can also include a receiver configured to receive the communications signal via the communications channel. A jitter creation module also can form part of the integrated circuit and can introduce jitter into the system thereby allowing for on-chip jitter testing. The jitter creation module can form either part of the transmitter or receiver and can introduce the jitter by phase interpolation.Type: GrantFiled: June 29, 2012Date of Patent: May 5, 2015Assignee: Broadcom CorporationInventors: John Wang, Vasudevan Parthasarathy
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Patent number: 8990654Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.Type: GrantFiled: December 20, 2013Date of Patent: March 24, 2015Assignee: Broadcom CorporationInventors: William Bliss, Vasudevan Parthasarathy
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Publication number: 20150070198Abstract: Systems and methods are provided for calibrating an analog to digital converter (ADC) using one or more feedback mechanisms. In an embodiment, a capture memory module captures a portion of ADC data and post-processes the captured data using a microprocessor to perform calibration. Using the microprocessor, the capture memory module calibrates the ADC until the output of the ADC is within a desired range. In an embodiment, the capture memory module also captures a portion of data output from a digital correction module and post-processes this captured data using the microprocessor.Type: ApplicationFiled: September 6, 2013Publication date: March 12, 2015Applicant: Broadcom CorporationInventors: John WANG, Vasudevan PARTHASARATHY
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Publication number: 20150063828Abstract: Systems that allow for DFE functionality to be eliminated from the receiver side of a communication system and for a DFE-like functionality to be implemented instead at the transmitter side of the communication system are provided. By removing the DFE functionality from the receiver side, error propagation can be eliminated at the receiver and receiver complexity can be reduced drastically. At the transmitter side, the DFE-like functionality provides the same DFE benefits, and with the transmitter environment being noise-free, no errors can occur due noise boosting, for example. The DFE-like functionality at the transmitter side can be implemented using non-linear (recursive or feed-forward) pre-coders or a combination of non-linear pre-coders and linear filters, which can be configured to invert a net communication channel between the transmitter and the receiver. Embodiments particularly suitable for fiber optic channels and server backplane channels are also provided.Type: ApplicationFiled: September 30, 2013Publication date: March 5, 2015Inventors: William BLISS, Vasudevan PARTHASARATHY
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Patent number: 8964907Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.Type: GrantFiled: April 26, 2013Date of Patent: February 24, 2015Assignee: Broadcom CorporationInventors: Vivek Pundlik Telang, Hong Chen, Vasudevan Parthasarathy, Jun Cao, Afshin Momtaz, Ali Ghiasi, Chung-Jue Chen
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Publication number: 20140112382Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.Type: ApplicationFiled: December 20, 2013Publication date: April 24, 2014Applicant: Broadcom CorporationInventors: William BLISS, Vasudevan PARTHASARATHY
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Patent number: 8661309Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.Type: GrantFiled: January 26, 2011Date of Patent: February 25, 2014Assignee: Broadcom CorporationInventors: William Bliss, Vasudevan Parthasarathy
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Publication number: 20130301691Abstract: Systems and methods that facilitate on-chip testing are provided. An integrated circuit can include a transmitter configured to transmit a communications signal via a communications channel. The integrated circuit can also include a receiver configured to receive the communications signal via the communications channel. A jitter creation module also can form part of the integrated circuit and can introduce jitter into the system thereby allowing for on-chip jitter testing. The jitter creation module can form either part of the transmitter or receiver and can introduce the jitter by phase interpolation.Type: ApplicationFiled: June 29, 2012Publication date: November 14, 2013Applicant: Broadcom CorporationInventors: John Wang, Vasudevan Parthasarathy
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Publication number: 20130243072Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.Type: ApplicationFiled: April 26, 2013Publication date: September 19, 2013Applicant: Broadcom CorporationInventors: Vivek Telang, Hong Chen, Vasudevan Parthasarathy, Jun Cao, Afshin Momtaz, Ali Ghiasi, Chung-Jue Chen
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Patent number: 8532163Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.Type: GrantFiled: February 6, 2012Date of Patent: September 10, 2013Assignee: Broadcom CorporationInventors: Abbas Amirichimeh, Howard Baumer, John Louie, Vasudevan Parthasarathy, Linda Ying
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Patent number: 8516331Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.Type: GrantFiled: January 26, 2011Date of Patent: August 20, 2013Assignee: Broadcom CorporationInventors: William Bliss, Vasudevan Parthasarathy
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Patent number: 8442159Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.Type: GrantFiled: September 16, 2010Date of Patent: May 14, 2013Assignee: Broadcom CorporationInventors: Vivek Telang, Hong Chen, Vasudevan Parthasarathy, Jun Cao, Afshin Momtaz, Ali Ghiasi, Chung-Jue Chen
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Publication number: 20120201280Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.Type: ApplicationFiled: February 6, 2012Publication date: August 9, 2012Applicant: Broadcom CorporationInventors: Abbas AMIRICHIMEH, Howard Baumer, John Louie, Vasudevan Parthasarathy, Linda Ying
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Patent number: 8111738Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.Type: GrantFiled: September 13, 2010Date of Patent: February 7, 2012Assignee: Broadcom CorporationInventors: Abbas Amirichimeh, Howard Baumer, John Louie, Vasudevan Parthasarathy, Linda Ying