Abstract: A method is presented that monitors the quality of a communications channel. The method includes receiving a data signal and establishing a zero reference phase of the received data signal. The method further includes generating a phase-shifted data signal by phase shifting the received data signal relative to the zero reference phase, and sampling the phase-shifted data signal for one or more phase-shift positions. A zero reference phase is reestablished between sampling at each of the phase-shift positions. The method also includes detecting bit errors in the phase-shifted data signal at each of the phase-shift positions in order to provide a communications channel quality measurement. In an embodiment, the method includes generating an eye diagram according to a count of detected bit errors relative to a count of detected bits. The eye diagram characterizes the quality of the communications channel.

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract: Embodiments include a decision feedback equalizer (DFE) circuit, including at least one reorder block configured to reorder a set of current sliced bit values based on one or more previous sliced bit values, and a selector configured to select one of the reordered current sliced bit values as a DFE output based on a group of non-adjacent DFE outputs.

Abstract: A system is presented that monitors the quality of a communications channel with mirror receivers. A first receiver and a second receiver, coupled in parallel with the first receiver, receive a data signal transmitted over the communications channel. The second receiver generates an output signal. A signal integrity (SI) processor manipulates the output signal in order to determine the quality of the communications channel. The SI processor samples a phase-shifted version of the output signal, which has a phase shifted relative to a zero reference phase, and analyzes the phase-shifted version of the output signal for bit errors. In an embodiment, the SI processor manipulates the output signal to extract an eye diagram indicative of the quality of the communications channel. The SI processor non-intrusively determines the quality of the communications channel using the second receiver.

Abstract: A trellis decoder system uses a feed-forward trellis demapping configuration to prevent error propagation. In a system for processing encoded binary data symbols representable as a symbol constellation, a decoder includes a delay for delaying received encoded symbol data. The decoder also includes a re-encoder for re-coding decoded symbol representative data and a processor for deriving decoded symbol data. The processor derives decoded symbol data using the delayed encoded symbol data and re-encoded data representative of a difference between successive symbols computed using an error propagation-free, feed-forward configuration.

Abstract: A communication receiver includes a decision feedback equalizer and clock and data recovery circuit. Various adaptation loops may control the operation of the decision feedback equalizer, the clock and data recovery circuit, a continuous time filter, a threshold adjust circuit, and an analog-to-digital clock that is used to generate soft decision data for some of the adaptation loops.

Abstract: Data error such as mean square error may be reduced in a system such as a communication receiver using a dithering algorithm that adjusts one or more parameters in the system. The dithering algorithm may be applied to more than one parameter. The dithering algorithm may include a state machine to alter the rate of change dependent on the state of the dithering algorithm.

Abstract: A method is presented that monitors the quality of a communications channel. The method includes receiving a data signal and establishing a zero reference phase of the received data signal. The method further includes generating a phase-shifted data signal by phase shifting the received data signal relative to the zero reference phase, and sampling the phase-shifted data signal for one or more phase-shift positions. A zero reference phase is reestablished between sampling at each of the phase-shift positions. The method also includes detecting bit errors in the phase-shifted data signal at each of the phase-shift positions in order to provide a communications channel quality measurement. In an embodiment, the method includes generating an eye diagram according to a count of detected bit errors relative to a count of detected bits. The eye diagram characterizes the quality of the communications channel.

Abstract: A system is presented that monitors the quality of a communications channel with mirror receivers. A first receiver and a second receiver, coupled in parallel with the first receiver, receive a data signal transmitted over the communications channel. The second receiver generates an output signal. A signal integrity (SI) processor manipulates the output signal in order to determine the quality of the communications channel. The SI processor samples a phase-shifted version of the output signal, which has a phase shifted relative to a zero reference phase, and analyzes the phase-shifted version of the output signal for bit errors. In an embodiment, the SI processor manipulates the output signal to extract an eye diagram indicative of the quality of the communications channel. The SI processor non-intrusively determines the quality of the communications channel using the second receiver.

Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Abstract: Systems and methods for synchronizing a receive clock signal phase with a transmit clock signal phase are presented. A system includes a receiving channel and a transmitting channel, wherein the transmitting channel synchronizes a transmit clock signal phase with a receive clock signal phase based on receive clock signal phase data. A method includes storing a previous receive clock signal phase of a receiving channel and identifying a current receive clock signal phase of the receiving channel. The method further includes determining a phase difference between the previous receive clock signal phase and the current receive clock signal phase, and identifying a direction of the phase difference between the previous receive clock signal phase and the current receive clock signal phase. The method further includes adjusting a previous transmit clock signal phase of the transmitting channel to a current transmit clock signal phase of the transmitting channel based on the phase difference and direction.

Abstract: An automatic polarity swap is implemented in a communications system. Two or more transceivers having differential inputs and outputs are coupled together through an interface, such as a backplane to form a communications system. In such a configuration, it is possible to cross-connect the differential data lines or signals at the interface, which will cause invalid data words to received at the second transceiver. Accordingly, the present invention includes an error check and correction module that detects invalid data words after parallel-to-serial conversion. More specifically, an error check determines if the parallel differential signal represents a valid data word. This can be done, for example, by storing and comparing valid data words in a memory such as RAM. If the received data word is valid, then no corrective action is taken.

Abstract: In a system for receiving a signal containing digital data representing HDTV image information in the form of multilevel symbols formatted into groups of successive fields, each field comprising a field segment, a plurality of data segments, and associated sync components, the received signal is demodulated to produce a demodulated signal. The demodulated signal is comb-filtered to reject NTSC co-channel interference to produce a filtered signal. The filtered signal is trellis decoded with a trellis decoder employing a truncated non-Euclidean metric.