Patents by Inventor Veena Misra
Veena Misra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220349871Abstract: The present disclosure presents environmental sensing apparatuses and methods. In one such apparatus, an environmental sensor comprises a substrate and an array of multiple metal oxide materials on the substrate. The multiple metal oxide materials can comprise layers of different metal oxide material, in which the multiple metal oxide materials are deposited on a cross-bar array of heater elements and electrodes and each row in the cross-bar array contains an independently-controlled heater element and each column in the array contains a pair of electrodes. At each crossing of the heater element and the pair of electrodes, one of the multiple metal oxide materials is deposited, and the pair of electrodes and the heater elements are dielectrically isolated from one another at the crossing.Type: ApplicationFiled: October 2, 2020Publication date: November 3, 2022Inventors: Bongmook Lee, Veena Misra
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Patent number: 10352914Abstract: An environmental stimulus sensor includes a substrate, a p-type material, and a conductive contact. In some aspects the conductive contact couples an electrode to the p-type material for supplying a current through the p-type material. The p-type material includes a nanotile structure for responding to an environmental stimulus by changing resistance.Type: GrantFiled: February 8, 2017Date of Patent: July 16, 2019Assignee: North Carolina State UniversityInventors: Bongmook Lee, Veena Misra
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Publication number: 20170227483Abstract: An environmental stimulus sensor can include a substrate, a p-type material, and a conductive contact. The conductive contact can couple an electrode to the p-type material for supplying a current through the p-type material. The p-type material can include a nanotile structure and can be coupled to the substrate for responding to an environmental stimulus at room temperature by changing resistance.Type: ApplicationFiled: February 8, 2017Publication date: August 10, 2017Inventors: Bongmook Lee, Veena Misra
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Patent number: 8529996Abstract: This invention provides a new procedure for attaching molecules to semiconductor surfaces, in particular silicon. The molecules, which include, but are not limited to porphyrins and ferrocenes, have been previously shown to be attractive candidates for molecular-based information storage. The new attachment procedure is simple, can be completed in short times, requires minimal amounts of material, is compatible with diverse molecular functional groups, and in some instances affords unprecedented attachment motifs. These features greatly enhance the integration of the molecular materials into the processing steps that are needed to create hybrid molecular/semiconductor information storage devices.Type: GrantFiled: March 19, 2007Date of Patent: September 10, 2013Assignees: The Regents of the University of California, North Carolina State UniversityInventors: David F. Bocian, Jonathan S. Lindsey, Zhiming Liu, Amir A. Yasseri, Veena Misra, Qian Zhao, Qiliang Li, Shyam Surthi, Robert S. Loewe
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Publication number: 20110147764Abstract: A metal-insulator-semiconductor field-effect transistor (MISFET) includes a semiconductor layer with source and drain regions of a first conductivity type spaced apart therein. A channel region of a first conductivity type extends between the source and drain regions. A gate contact is on the channel region. A dielectric channel depletion layer is between the gate contact and the channel region. The dielectric channel depletion layer provides a net charge having the same polarity as the first conductivity type charge carriers, and which may deplete the first conductivity type charge carriers from an adjacent portion of the channel region when no voltage is applied to the gate contact.Type: ApplicationFiled: November 4, 2009Publication date: June 23, 2011Inventors: Sarit Dhar, Sei-Hyung Ryu, Veena Misra, Daniel J. Lichtenwalner
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Patent number: 7642546Abstract: According to some embodiments, an article of manufacture comprises a substrate; a molecular layer on the substrate comprising at least one charge storage molecule coupled to the substrate by a molecular linker; a solid barrier dielectric layer directly on the molecular layer; and a conductive layer directly on the solid barrier dielectric layer. In some embodiments, the solid barrier dielectric layer is configured to provide a voltage drop across the molecular layer that is greater than a voltage drop across the solid barrier dielectric layer when a voltage is applied to the conductive layer. In some embodiments, the molecular layer has a thickness greater than that of the solid barrier dielectric layer. The article of manufacture contains no electrolyte between the molecular layer and the conductive layer.Type: GrantFiled: November 30, 2006Date of Patent: January 5, 2010Assignees: Zettacore, Inc., North Carolina State UniversityInventors: Veena Misra, Ritu Shrivastava, Zhong Chen, Guru Mathur
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Patent number: 7312100Abstract: This invention pertains to methods assembly of organic molecules and electrolytes in hybrid electronic. In one embodiment, a method is provided that involves contacting a surface/electrode with a compound of formula: R-L2-M-L1-Z1 where Z1 is a surface attachment group; L1 and L2 are independently linker or covalent bonds; M is an information storage molecule; and R is a protected or unprotected reactive site or group; where the contacting results in attachment of the redox-active moiety to the surface via the surface attachment group; and ii) contacting the surface-attached information storage molecule with an electrolyte having the formula: J-Q where J is a charged moiety (e.g., an electrolyte); and Q is a reactive group that is reactive with the reactive group (R) and attaches J to the information storage molecule thereby patterning the electrolyte on the surface.Type: GrantFiled: April 30, 2004Date of Patent: December 25, 2007Assignee: The North Carolina State UniversityInventors: David F. Bocian, Werner G. Kuhr, Jonathan S. Lindsey, Veena Misra
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Publication number: 20070212897Abstract: This invention provides a new procedure for attaching molecules to semiconductor surfaces, in particular silicon. The molecules, which include, but are not limited to porphyrins and ferrocenes, have been previously shown to be attractive candidates for molecular-based information storage. The new attachment procedure is simple, can be completed in short times, requires minimal amounts of material, is compatible with diverse molecular functional groups, and in some instances affords unprecedented attachment motifs. These features greatly enhance the integration of the molecular materials into the processing steps that are needed to create hybrid molecular/semiconductor information storage devices.Type: ApplicationFiled: March 19, 2007Publication date: September 13, 2007Applicants: The Regents of the University of California, North Carolina State UniversityInventors: David Bocian, Jonathan Lindsey, Zhiming Liu, Amir Yasseri, Veena Misra, Qian Zhao, Qiliang Li, Shyam Surthi, Robert Loewe
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Patent number: 7265375Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.Type: GrantFiled: February 24, 2005Date of Patent: September 4, 2007Assignee: North Carolina State UniversityInventors: Zhibo Zhang, Veena Misra, Salah M. A. Bedair, Mehmet Ozturk
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Patent number: 7253466Abstract: The present invention provides microelectronic electrochemical structures and related fabrication methods. A composite microelectronic structure is provided that includes first and second conductors dielectrically isolated from one another at a crossing thereof, the crossing surrounded by a dielectric material. A portion of the dielectric material around the crossing of the first and second conductors is removed to form a well that exposes respective outer surfaces of the first and second conductors and a molecule is deposited in the well such that the deposited molecule contacts the exposed outer surfaces of the first and second conductors.Type: GrantFiled: June 24, 2005Date of Patent: August 7, 2007Assignee: North Carolina State UniversityInventors: Veena Misra, John Damiano, Jr.
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Publication number: 20070164374Abstract: According to some embodiments, an article of manufacture comprises a substrate; a molecular layer on the substrate comprising at least one charge storage molecule coupled to the substrate by a molecular linker; a solid barrier dielectric layer directly on the molecular layer; and a conductive layer directly on the solid barrier dielectric layer. In some embodiments, the solid barrier dielectric layer is configured to provide a voltage drop across the molecular layer that is greater than a voltage drop across the solid barrier dielectric layer when a voltage is applied to the conductive layer. In some embodiments, the molecular layer has a thickness greater than that of the solid barrier dielectric layer. The article of manufacture contains no electrolyte between the molecular layer and the conductive layer.Type: ApplicationFiled: November 30, 2006Publication date: July 19, 2007Inventors: Veena Misra, Ritu Shrivastava, Zhong Chen, Guru Mathur
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Patent number: 7211458Abstract: A method of fabricating a semiconductor device includes forming a strained first semiconductor layer on an insulating layer that is between second semiconductor layers. The strained first semiconductor layer may be epitaxially grown from the second semiconductor layers to extend onto the insulating layer between the second semiconductor layers. The second semiconductor layers have a lattice constant that is different than that of the first semiconductor layer, such that strain may be created in the first semiconductor layer. Related devices are also discussed.Type: GrantFiled: August 8, 2005Date of Patent: May 1, 2007Assignee: North Carolina State UniversityInventors: Mehmet Ozturk, Veena Misra, Saurabh Chopra
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Publication number: 20070029553Abstract: A method of fabricating a semiconductor device includes forming a strained first semiconductor layer on an insulating layer that is between second semiconductor layers. The strained first semiconductor layer may be epitaxially grown from the second semiconductor layers to extend onto the insulating layer between the second semiconductor layers. The second semiconductor layers have a lattice constant that is different than that of the first semiconductor layer, such that strain may be created in the first semiconductor layer. Related devices are also discussed.Type: ApplicationFiled: August 8, 2005Publication date: February 8, 2007Inventors: Mehmet Ozturk, Veena Misra, Saurabh Chopra
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Publication number: 20050242389Abstract: The present invention provides microelectronic electrochemical structures and related fabrication methods. A composite microelectronic structure is provided that includes first and second conductors dielectrically isolated from one another at a crossing thereof, the crossing surrounded by a dielectric material. A portion of the dielectric material around the crossing of the first and second conductors is removed to form a well that exposes respective outer surfaces of the first and second conductors and a molecule is deposited in the well such that the deposited molecule contacts the exposed outer surfaces of the first and second conductors.Type: ApplicationFiled: June 24, 2005Publication date: November 3, 2005Inventors: Veena Misra, John Damiano
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Patent number: 6958485Abstract: The present invention provides hybrid microelectronic memory device, comprising: (a) a substrate having a surface, a first region of first work function adjacent the surface, and a second region of second work function adjacent the surface and adjacent the first region; (b) a film comprising redox-active molecules on the first and second regions; and (c) an electrode connected to the film. The present invention further provides a hybrid microelectronic memory device, comprising: (a) a substrate having surface and a structure or region such as a diode for increasing the retention time of the device formed adjacent the surface; (b) a film comprising redox-active molecules on or associated with the region or structure; and (c) an electrode connected to the redox active molecules opposite the substrate surface. Methods of using such devices are also described.Type: GrantFiled: December 5, 2003Date of Patent: October 25, 2005Assignee: North Carolina State UniversityInventors: Veena Misra, Srivardhan Gowda, Guru Mathur
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Patent number: 6958270Abstract: The present invention provides microelectronic electrochemical structures and related fabrication methods. A composite microelectronic structure is provided that includes first and second conductors dielectrically isolated from one another at a crossing thereof, the crossing surrounded by a dielectric material. A portion of the dielectric material around the crossing of the first and second conductors is removed to form a well that exposes respective outer surfaces of the first and second conductors and a molecule is deposited in the well such that the deposited molecule contacts the exposed outer surfaces of the first and second conductors.Type: GrantFiled: April 4, 2003Date of Patent: October 25, 2005Assignee: North Carolina State UniversityInventors: Veena Misra, John Damiano, Jr.
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Publication number: 20050207208Abstract: This invention pertains to methods assembly of organic molecules and electrolytes in hybrid electronic. In one embodiment, a is provided that involves contacting a surface/electrode with a compound if formula: R-L2-M-L1-Z1 where Z1 is a surface attachment group; L1 and L2 are independently linker or covalent bonds; M is an information storage molecule; and R is a protected or unprotected reactive site or group; where the contacting results in attachment of the redox-active moiety to the surface via the surface attachment group; and ii) contacting the surface-attached information storage molecule with an electrolyte having the formula: J-Q where J is a charged moiety (e.g., an electrolyte); and Q is a reactive group that is reactive with the reactive group (R) and attaches J to the information storage molecule thereby patterning the electrolyte on the surface.Type: ApplicationFiled: April 30, 2004Publication date: September 22, 2005Inventors: David Bocian, Werner Kuhr, Jonathan Lindsey, Veena Misra
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Publication number: 20050156180Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.Type: ApplicationFiled: February 24, 2005Publication date: July 21, 2005Inventors: Zhibo Zhang, Veena Misra, Salah Bedair, Mehmet Ozturk
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Patent number: 6914256Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.Type: GrantFiled: January 20, 2004Date of Patent: July 5, 2005Assignee: North Carolina State UniversityInventors: Zhibo Zhang, Veena Misra, Salah M. A. Bedair, Mehmet Ozturk
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Publication number: 20050121660Abstract: The present invention provides hybrid microelectronic memory device, comprising: (a) a substrate having a surface, a first region of first work function adjacent the surface, and a second region of second work function adjacent the surface and adjacent the first region; (b) a film comprising redox-active molecules on the first and second regions; and (c) an electrode connected to the film. The present invention further provides a hybrid microelectronic memory device, comprising: (a) a substrate having surface and a structure or region such as a diode for increasing the retention time of the device formed adjacent the surface; (b) a film comprising redox-active molecules on or associated with the region or structure; and (c) an electrode connected to the redox active molecules opposite the substrate surface. Methods of using such devices are also described.Type: ApplicationFiled: December 5, 2003Publication date: June 9, 2005Inventors: Veena Misra, Srivardhan Gowda, Guru Mathur