Abstract: Integrated circuit electrodes include an alloy of a first metal and a second metal having lower work function than the first metal. The second metal also may have higher oxygen affinity than the first metal. The first metal may be Ru, Ir, Os, Re and alloys thereof, and the second metal may be Ta, Nb, Al, Hf, Zr, La and alloys thereof. Both NMOS and the PMOS devices can include gate electrodes of an alloy of the first metal and the second metal having lower work function than the first metal. The PMOS gate electrode may have a higher percentage of the first metal relative to the second metal than the NMOS gate electrode. Thus, a common material system may be used for gate electrodes for both NMOS and PMOS devices.

Abstract: A method and/or system and/or apparatus for a molecular-based FET device (an m-FET) uses charge storing molecules (120) between a gate (110) and channel (105) of an FET-type transistor. Further embodiments describe fabrication methods for using combinations of standard practices in lithography and synthetic chemistry and novel elements.

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

Abstract: The present invention provides microelectronic electrochemical structures and related fabrication methods. A composite microelectronic structure is provided that includes first and second conductors dielectrically isolated from one another at a crossing thereof, the crossing surrounded by a dielectric material. A portion of the dielectric material around the crossing of the first and second conductors is removed to form a well that exposes respective outer surfaces of the first and second conductors and a molecule is deposited in the well such that the deposited molecule contacts the exposed outer surfaces of the first and second conductors.

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

Abstract: A method and/or system and/or apparatus for a molecular-based FET device (an m-FET) uses charge storing molecules between a gate and channel of an FET-type transistor. Further embodiments describe fabrication methods for using combinations of standard practices in lithography and synthetic chemistry and novel elements.

Abstract: Integrated circuit electrodes include an alloy of a first metal and a second metal having lower work function than the first metal. The second metal also may have higher oxygen affinity than the first metal. The first metal may be Ru, Ir, Os, Re and alloys thereof, and the second metal may be Ta, Nb, Al, Hf, Zr, La and alloys thereof. Both NMOS and the PMOS devices can include gate electrodes of an alloy of the first metal and the second metal having lower work function than the first metal. The PMOS gate electrode may have a higher percentage of the first metal relative to the second metal than the NMOS gate electrode. Thus, a common material system may be used for gate electrodes for both NMOS and PMOS devices.

Abstract: A method and/or system and/or apparatus for a molecular-based FET device (an m-FET) uses charge storing molecules between a gate and channel of an FET-type transistor. Further embodiments describe fabrication methods for using combinations of standard practices in lithography and synthetic chemistry and novel elements.

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

Abstract: A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (24 or 108). After formation of the source and drain regions, the features (24 and 108 are processed to fill these features with a metallic gate layer (28a or 128a). This metal layer (28a or 128a) is then chemically mechanically polished (CMPed) to form a metallic plug region (28b or 128b) within the features (24 or 108). The plug region (28b or 128b) is formed in either an inlaid or dual inlaid manner wherein this metallic plug region (28b or 128b) is self-aligned to the previously formed source and drain regions and preferably functions as a metal MOS gate region.