Patents by Inventor Veeraraghavan Basker
Veeraraghavan Basker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11887890Abstract: Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided.Type: GrantFiled: December 17, 2021Date of Patent: January 30, 2024Assignee: International Business Machines CorporationInventors: Ruilong Xie, Veeraraghavan Basker, Alexander Reznicek, Junli Wang
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Patent number: 11862710Abstract: A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.Type: GrantFiled: January 6, 2022Date of Patent: January 2, 2024Assignee: International Business Machines CorporationInventors: Chun-Chen Yeh, Alexander Reznicek, Veeraraghavan Basker, Junli Wang
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Patent number: 11349001Abstract: A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact.Type: GrantFiled: October 10, 2019Date of Patent: May 31, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruilong Xie, Carl Radens, Kangguo Cheng, Veeraraghavan Basker, Juntao Li
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Publication number: 20220130980Abstract: A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.Type: ApplicationFiled: January 6, 2022Publication date: April 28, 2022Inventors: Chun-Chen Yeh, Alexander Reznicek, Veeraraghavan Basker, Junli Wang
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Publication number: 20220108923Abstract: Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided.Type: ApplicationFiled: December 17, 2021Publication date: April 7, 2022Inventors: Ruilong Xie, Veeraraghavan Basker, Alexander Reznicek, Junli Wang
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Patent number: 11239343Abstract: A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.Type: GrantFiled: February 21, 2020Date of Patent: February 1, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chun-Chen Yeh, Alexander Reznicek, Veeraraghavan Basker, Junli Wang
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Patent number: 11239115Abstract: Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided.Type: GrantFiled: October 30, 2019Date of Patent: February 1, 2022Assignee: International Business Machines CorporationInventors: Ruilong Xie, Veeraraghavan Basker, Alexander Reznicek, Junli Wang
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Patent number: 11183558Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a nanosheet field effect transistor (FET) device. The fabrication operations include forming a nanosheet stack over a portion of a substrate. A first source or drain (S/D) trench is formed adjacent to a first end of the nanosheet stack. A second S/D trench is formed adjacent to a second end of the nanosheet stack. A region of the substrate is removed to form a bottom dielectric isolation (BDI) cavity in the substrate, wherein the BDI cavity is positioned beneath at least the nanosheet stack, the first S/D trench, and the second S/D trench. The BDI cavity is filled with a dielectric material, thereby forming a BDI region positioned beneath at least the nanosheet stack, the first S/D trench, and the second S/D trench.Type: GrantFiled: February 10, 2020Date of Patent: November 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chun-Chen Yeh, Veeraraghavan Basker, Alexander Reznicek, Junli Wang
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Publication number: 20210265488Abstract: A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.Type: ApplicationFiled: February 21, 2020Publication date: August 26, 2021Inventors: Chun-Chen Yeh, Alexander Reznicek, Veeraraghavan Basker, Junli Wang
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Publication number: 20210249506Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a nanosheet field effect transistor (FET) device. The fabrication operations include forming a nanosheet stack over a portion of a substrate. A first source or drain (S/D) trench is formed adjacent to a first end of the nanosheet stack. A second S/D trench is formed adjacent to a second end of the nanosheet stack. A region of the substrate is removed to form a bottom dielectric isolation (BDI) cavity in the substrate, wherein the BDI cavity is positioned beneath at least the nanosheet stack, the first S/D trench, and the second S/D trench. The BDI cavity is filled with a dielectric material, thereby forming a BDI region positioned beneath at least the nanosheet stack, the first S/D trench, and the second S/D trench.Type: ApplicationFiled: February 10, 2020Publication date: August 12, 2021Inventors: Chun-Chen Yeh, Veeraraghavan Basker, Alexander Reznicek, Junli Wang
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Patent number: 11024536Abstract: Embodiments of the present invention are directed to reducing the effective capacitance between active devices at the contact level. In a non-limiting embodiment of the invention, an interlayer dielectric is replaced with a low-k material without damaging a self-aligned contact (SAC) cap. A gate can be formed over a channel region of a fin. The gate can include a gate spacer and a SAC cap. Source and drain regions can be formed adjacent to the channel region. A contact is formed on the SAC cap and on surfaces of the source and drain regions. A first dielectric layer can be recessed to expose a sidewall of the contact and a sidewall of the gate spacer. A second dielectric layer can be formed on the recessed surface of the first dielectric layer. The second dielectric layer can include a dielectric material having a dielectric constant less than the first dielectric layer.Type: GrantFiled: April 18, 2019Date of Patent: June 1, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Adra Carr, Vimal Kamineni, Ruilong Xie, Andrew Greene, Nigel Cave, Veeraraghavan Basker
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Publication number: 20210134671Abstract: Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided.Type: ApplicationFiled: October 30, 2019Publication date: May 6, 2021Inventors: Ruilong Xie, Veeraraghavan Basker, Alexander Reznicek, Junli Wang
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Patent number: 10998234Abstract: Embodiments of the present invention are directed to a method that prevents punch-through of a bottom isolation layer and improves the quality of the source/drain epitaxial growth in a nanosheet semiconductor structure. In a non-limiting embodiment of the invention, a bottom isolation structure is formed over a substrate. The bottom isolation structure includes a tri-layer stack in a first region of the substrate and a bi-layer stack in a second region of the substrate. A nanosheet stack is formed over the bottom isolation structure in the first region of the substrate. A gate is formed over a channel region of the nanosheet stack.Type: GrantFiled: May 14, 2019Date of Patent: May 4, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruilong Xie, Veeraraghavan Basker, Nicolas Loubet, Balasubramanian Pranatharthiharan
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Publication number: 20210111028Abstract: A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact.Type: ApplicationFiled: October 10, 2019Publication date: April 15, 2021Inventors: Ruilong Xie, Carl Radens, Kangguo Cheng, Veeraraghavan Basker, Juntao LI
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Patent number: 10943990Abstract: Gate contact over active layout designs are provided. In one aspect, a method for forming a gate contact over active device includes: forming a device including metal gates over an active area of a wafer, and source/drains on opposite sides of the metal gates offset by gate spacers; recessing the metal gates/gate spacers; forming etch-selective spacers on top of the recessed gate spacers; forming gate caps on top of the recessed metal gates; forming source/drain contacts on the source/drains; forming source/drain caps on top of the source/drain contacts, wherein the etch-selective spacers provide etch selectivity to the gate caps and source/drain caps; and forming a metal gate contact that extends through one of the gate caps, wherein the etch-selective spacers prevent gate-to-source drain shorting by the metal gate contact. Alternate etch-selective configurations are also provided including a claw-shaped source/drain cap design. A gate contact over active device is also provided.Type: GrantFiled: October 25, 2018Date of Patent: March 9, 2021Assignee: International Business Machines CorporationInventors: Andrew Greene, Victor W. C. Chan, Gangadhara Raja Muthinti, Veeraraghavan Basker, Junli Wang, Kisik Choi, Su Chen Fan
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Patent number: 10872809Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above at least an active region, wherein the gate structure has an axial length in a direction corresponding to a gate width direction of the transistor device. In this example, a first portion of the axial length of the gate structure has a first upper surface and a second portion of the axial length of the gate structure has a second upper surface, wherein the first upper surface is positioned at a level that is above a level of the second upper surface. The device also includes a gate contact structure that contacts the first upper surface of the gate structure.Type: GrantFiled: September 23, 2019Date of Patent: December 22, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Lars W. Liebmann, Balasubramanian Pranatharthi Haran, Veeraraghavan Basker
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Publication number: 20200365687Abstract: Embodiments of the present invention are directed to a method that prevents punch-through of a bottom isolation layer and improves the quality of the source/drain epitaxial growth in a nanosheet semiconductor structure. In a non-limiting embodiment of the invention, a bottom isolation structure is formed over a substrate. The bottom isolation structure includes a tri-layer stack in a first region of the substrate and a bi-layer stack in a second region of the substrate. A nanosheet stack is formed over the bottom isolation structure in the first region of the substrate. A gate is formed over a channel region of the nanosheet stack.Type: ApplicationFiled: May 14, 2019Publication date: November 19, 2020Inventors: Ruilong Xie, Veeraraghavan Basker, Nicolas Loubet, Balasubramanian Pranatharthiharan
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Publication number: 20200335392Abstract: Embodiments of the present invention are directed to reducing the effective capacitance between active devices at the contact level. In a non-limiting embodiment of the invention, an interlayer dielectric is replaced with a low-k material without damaging a self-aligned contact (SAC) cap. A gate can be formed over a channel region of a fin. The gate can include a gate spacer and a SAC cap. Source and drain regions can be formed adjacent to the channel region. A contact is formed on the SAC cap and on surfaces of the source and drain regions. A first dielectric layer can be recessed to expose a sidewall of the contact and a sidewall of the gate spacer. A second dielectric layer can be formed on the recessed surface of the first dielectric layer. The second dielectric layer can include a dielectric material having a dielectric constant less than the first dielectric layer.Type: ApplicationFiled: April 18, 2019Publication date: October 22, 2020Inventors: Adra Carr, Vimal Kamineni, Ruilong Xie, Andrew Greene, Nigel Cave, Veeraraghavan Basker
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Publication number: 20200135886Abstract: Gate contact over active layout designs are provided. In one aspect, a method for forming a gate contact over active device includes: forming a device including metal gates over an active area of a wafer, and source/drains on opposite sides of the metal gates offset by gate spacers; recessing the metal gates/gate spacers; forming etch-selective spacers on top of the recessed gate spacers; forming gate caps on top of the recessed metal gates; forming source/drain contacts on the source/drains; forming source/drain caps on top of the source/drain contacts, wherein the etch-selective spacers provide etch selectivity to the gate caps and source/drain caps; and forming a metal gate contact that extends through one of the gate caps, wherein the etch-selective spacers prevent gate-to-source drain shorting by the metal gate contact. Alternate etch-selective configurations are also provided including a claw-shaped source/drain cap design. A gate contact over active device is also provided.Type: ApplicationFiled: October 25, 2018Publication date: April 30, 2020Inventors: Andrew Greene, Victor W.C. Chan, Gangadhara Raja Muthinti, Veeraraghavan Basker, Junli Wang, Kisik Choi, Su Chen Fan
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Patent number: 10586739Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.Type: GrantFiled: October 27, 2017Date of Patent: March 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang