Patents by Inventor Veeraraghavan Basker
Veeraraghavan Basker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200020575Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above at least an active region, wherein the gate structure has an axial length in a direction corresponding to a gate width direction of the transistor device. In this example, a first portion of the axial length of the gate structure has a first upper surface and a second portion of the axial length of the gate structure has a second upper surface, wherein the first upper surface is positioned at a level that is above a level of the second upper surface. The device also includes a gate contact structure that contacts the first upper surface of the gate structure.Type: ApplicationFiled: September 23, 2019Publication date: January 16, 2020Inventors: Ruilong Xie, Lars W. Liebmann, Balasubramanian Pranatharthi Haran, Veeraraghavan Basker
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Patent number: 10522639Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.Type: GrantFiled: June 29, 2019Date of Patent: December 31, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Daniel Jaeger, Haigou Huang, Veeraraghavan Basker, Christopher Nassar, Jinsheng Gao, Michael Aquilino
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Patent number: 10497612Abstract: One illustrative method disclosed includes, among other things, forming at least one layer of sacrificial material above an underlying conductive structure, forming a sacrificial contact structure in the at least one layer of sacrificial material and forming at least one layer of insulating material around the sacrificial contact structure. In this example, the method also includes performing at least one process operation to expose an upper surface of the sacrificial contact structure, removing the sacrificial contact structure so as to form a contact opening that exposes the upper surface of the underlying conductive structure and forming a final contact structure in the contact opening, the final contact structure conductively contacting the underlying conductive structure.Type: GrantFiled: December 11, 2017Date of Patent: December 3, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Lars W. Liebmann, Balasubramanian Pranatharthi Haran, Veeraraghavan Basker
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Patent number: 10497629Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.Type: GrantFiled: November 2, 2016Date of Patent: December 3, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
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Publication number: 20190326408Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.Type: ApplicationFiled: June 29, 2019Publication date: October 24, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Daniel Jaeger, Haigou Huang, Veeraraghavan Basker, Christopher Nassar, Jinsheng Gao, Michael Aquilino
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Patent number: 10418455Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.Type: GrantFiled: September 26, 2017Date of Patent: September 17, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Daniel Jaeger, Haigou Huang, Veeraraghavan Basker, Christopher Nassar, Jinsheng Gao, Michael Aquilino
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Publication number: 20190181042Abstract: One illustrative method disclosed includes, among other things, forming at least one layer of sacrificial material above an underlying conductive structure, forming a sacrificial contact structure in the at least one layer of sacrificial material and forming at least one layer of insulating material around the sacrificial contact structure. In this example, the method also includes performing at least one process operation to expose an upper surface of the sacrificial contact structure, removing the sacrificial contact structure so as to form a contact opening that exposes the upper surface of the underlying conductive structure and forming a final contact structure in the contact opening, the final contact structure conductively contacting the underlying conductive structure.Type: ApplicationFiled: December 11, 2017Publication date: June 13, 2019Inventors: Ruilong Xie, Lars W. Liebmann, Balasubramanian Pranatharthi Haran, Veeraraghavan Basker
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Publication number: 20190097015Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.Type: ApplicationFiled: September 26, 2017Publication date: March 28, 2019Applicant: GLOBALFOUDRIES INC.Inventors: Hui Zang, Daniel Jaeger, Haigou Huang, Veeraraghavan Basker, Christopher Nassar, Jinsheng Gao, Michael Aquilino
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Publication number: 20180047637Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.Type: ApplicationFiled: October 27, 2017Publication date: February 15, 2018Inventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
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Patent number: 9805987Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.Type: GrantFiled: September 4, 2015Date of Patent: October 31, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
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Patent number: 9627278Abstract: A method of forming field effect transistors (FETs), and forming integrated circuit (IC) chip including the FETs. Gates are formed on said semiconductor fins to define multi fin field effect transistors (FinFETs). Dielectric sidewalls on fins protect the sidewalls while the surface is damaged intentionally, e.g., with an implant that leaves source/drain junctions undisturbed. After removing the dielectric sidewalls semiconductor material is grown epitaxially on the sidewalls with the damage retarding growth on the surface. The epi-growth bridges between fins in the same FET. After the damage is repaired, chip processing continues normally.Type: GrantFiled: June 16, 2015Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventors: Veeraraghavan Basker, Kangguo Cheng, Ali Khakifirooz
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Publication number: 20170076993Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.Type: ApplicationFiled: November 2, 2016Publication date: March 16, 2017Inventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
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Publication number: 20170069549Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.Type: ApplicationFiled: September 4, 2015Publication date: March 9, 2017Inventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
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Patent number: 9559014Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.Type: GrantFiled: November 24, 2015Date of Patent: January 31, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
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Publication number: 20160372383Abstract: A method of forming field effect transistors (FETs), and forming integrated circuit (IC) chip including the FETs. Gates are formed on said semiconductor fins to define multi fin field effect transistors (FinFETs). Dielectric sidewalls on fins protect the sidewalls while the surface is damaged intentionally, e.g., with an implant that leaves source/drain junctions undisturbed. After removing the dielectric sidewalls semiconductor material is grown epitaxially on the sidewalls with the damage retarding growth on the surface. The epi-growth bridges between fins in the same FET. After the damage is repaired, chip processing continues normally.Type: ApplicationFiled: June 16, 2015Publication date: December 22, 2016Applicant: International Business Machines CorporationInventors: Veeraraghavan Basker, Kangguo Cheng, Ali Khakifirooz
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Patent number: 9379025Abstract: A method of forming field effect transistors (FETs), and forming integrated circuit (IC) chip including the FETs. After forming replacement metal gate (RMG) FinFETs on a surface layer of a silicon on insulator (SOI) wafer, and growing unmerged epitaxially (epi) on the fins, the epi is capped with dielectric and an inter-level dielectric (ILD) layer is formed on the SOI wafer. The said ILD layer is patterned to an upper surface of the epi above encased fins in a timed etch. Then, etching, preferably with an etchant selective to silicon, the epi is opened to, and into, the fins. The resulting orifices are filled with conductive material to form source drain contacts.Type: GrantFiled: June 19, 2015Date of Patent: June 28, 2016Assignee: International Business Machines CorporationInventors: Veeraraghavan Basker, Kangguo Cheng, Ali Khakifirooz
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Patent number: 9373618Abstract: A technique relates to forming a semiconductor device. A field-effect transistor structure having a substrate, a fin structure patterned in the substrate, a gate stack structure, and an insulator layer is first provided. A non-capacitor region and a capacitor region are then formed on the field-effect transistor structure by masking portions of the field-effect transistor structure with a mask such that a non-capacitor region is masked and a capacitor region is exposed, and etching the insulator layer to further recess the fin structure and gate stack structure within the capacitor region such that a revealed height of the fins within the capacitor region is increased relative to the revealed height of the fins in the non-capacitor region. A high-k layer can be deposited over the recessed fins and gate stack structures and a gate metal can fill the recessed portions therein.Type: GrantFiled: September 4, 2015Date of Patent: June 21, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
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Patent number: 9337254Abstract: A technique relates to forming a semiconductor device. A field-effect transistor structure having a substrate, a fin structure patterned in the substrate, a gate stack structure, and an insulator layer is first provided. A non-capacitor region and a capacitor region are then formed on the field-effect transistor structure by masking portions of the field-effect transistor structure with a mask such that a non-capacitor region is masked and a capacitor region is exposed, and etching the insulator layer to further recess the fin structure and gate stack structure within the capacitor region such that a revealed height of the fins within the capacitor region is increased relative to the revealed height of the fins in the non-capacitor region. A high-k layer can be deposited over the recessed fins and gate stack structures and a gate metal can fill the recessed portions therein.Type: GrantFiled: November 24, 2015Date of Patent: May 10, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
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Patent number: 9324842Abstract: A method for fabricating a finfet with a buried local interconnect and the resulting device are disclosed. Embodiments include forming a silicon fin on a BOX layer, forming a gate electrode perpendicular to the silicon fin over a portion of the silicon fin, forming a spacer on each of opposite sides of the gate electrode, forming source/drain regions on the silicon fin at opposite sides of the gate electrode, recessing the BOX layer, undercutting the silicon fin and source/drain regions, at opposite sides of the gate electrode, and forming a local interconnect on a recessed portion of the BOX layer.Type: GrantFiled: December 20, 2013Date of Patent: April 26, 2016Assignees: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hui Zang, Chun-chen Yeh, Tenko Yamashita, Veeraraghavan Basker
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Publication number: 20150179766Abstract: A method for fabricating a finfet with a buried local interconnect and the resulting device are disclosed. Embodiments include forming a silicon fin on a BOX layer, forming a gate electrode perpendicular to the silicon fin over a portion of the silicon fin, forming a spacer on each of opposite sides of the gate electrode, forming source/drain regions on the silicon fin at opposite sides of the gate electrode, recessing the BOX layer, undercutting the silicon fin and source/drain regions, at opposite sides of the gate electrode, and forming a local interconnect on a recessed portion of the BOX layer.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Inventors: Hui ZANG, Chun-chen YEH, Tenko YAMASHITA, Veeraraghavan BASKER