Abstract: The present invention discloses an advanced pet-monitoring system including at least one of wearable component and the connected user device. The system utilizes data collected from each of these components as well as the state of any connections between the devices to (i) make various determinations about the pet's health and environment; (ii) notify the user of substantial changes in the pet's health and environment; and (iii) track the location of the pet.

Abstract: Disclosed embodiments relate, generally, to improved data reception handling at a physical layer. Some embodiments relate to end of line systems that include legacy media access control (MAC) devices and PHY devices that implement improved data reception handling disclosed herein. The improved data reception handling improves the operation of legacy systems, and the MAC more specifically, and in some cases to comply with media access tuning protocols implemented at the physical layer.

Abstract: A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

Abstract: A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

Abstract: A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

Abstract: A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

Abstract: A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

Abstract: A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

Abstract: Methods include receiving at least one electronic device including a sensor or an emitter, placing a cover over the sensor or emitter, placing the electronic device, including the cover, into a transfer mold system, encapsulating the electronic device with charge material, and removing a portion of the encapsulating charge material and the cover to expose the sensor or emitter to the environment.

Abstract: Various examples relate to a wired local area network (WLAN) including a shared transmission medium. An apparatus includes a beacon counter and an operational mode controller. The beacon counter is operably coupled to a line of a shared transmission medium of a wired local area network. The beacon counter is to count beacon signals on the line and determine a beacon count over a predetermined time period, or a beacon rate of the beacon signals. The operational mode controller is to control the apparatus to take over operation as a master node of the wired local area network based, at least in part, on a maximum bus cycle length of bus cycles on the line and responsive to the beacon count or the beacon rate.

Abstract: Methods include receiving at least one electronic device including a sensor or an emitter, placing a cover over the sensor or emitter, placing the electronic device, including the cover, into a transfer mold system, encapsulating the electronic device with charge material, and removing a portion of the encapsulating charge material and the cover to expose the sensor or emitter to the environment.

Abstract: A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

Abstract: A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

Abstract: The present invention discloses composition comprising an open matrix network carrying pharmaceutically active cannabinoid substance, pharmaceutically acceptable water soluble or water dispersible carrier materials provided as discrete units of the suspension or emulsion in form of liquid units contained in pockets of suitable mould, solid units such as frozen units, gelled units or frozen discrete units, wherein the composition is in the form chosen from sublingual tablet, buccal tablet, and rapidly disintegrating tablet.

Abstract: Disclosed embodiments relate, generally, to improved data reception handling at a physical layer. Some embodiments relate to end of line systems that include legacy media access control (MAC) devices and PHY devices that implement improved data reception handling disclosed herein. The improved data reception handling improves the operation of legacy systems, and the MAC more specifically, and in some cases to comply with media access tuning protocols implemented at the physical layer.

Abstract: Methods include receiving at least one electronic device including a sensor or an emitter, placing a cover over the sensor or emitter, placing the electronic device, including the cover, into a transfer mold system, encapsulating the electronic device with charge material, and removing a portion of the encapsulating charge material and the cover to expose the sensor or emitter to the environment.

Abstract: A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

Abstract: A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

Abstract: In accordance with one embodiment, a computer-implemented method is provided, comprising the act of: configuring code or hardware to cause at least part of the hardware to operate as a double data rate (DDR) memory controller and to: produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of: at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

Abstract: A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation.