Abstract: In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: generate a core clock; generate a capture clock; receive a data (DQ) signal that is driven by a DDR memory, or a signal derived from the DQ signal; clock a first core domain register, based, at least in part, on the capture clock; clock a second core domain register, based, at least in part, on the core clock; and set a delay of a core clock delay element, utilizing at least one of: the first core domain register, a signal derived from the first core domain register, the second core domain register, or a signal derived from the second core domain register; wherein the double data rate (DDR) memory controller is configured such that the delay of the core clock delay element is set during a power-on initialization calibration operation.

Abstract: A method for calibrating capturing read data in a read data path for a DDR memory interface circuit is described. In one version, the method includes the steps of delaying a core clock signal by a capture clock delay value to produce a capture clock signal and determining the capture clock delay value. The capture clock signal is a delayed version of the core clock signal. The timing for the read data path with respect to data propagation is responsive to at least the capture clock signal. In another version, timing for data capture is responsive to a read data strobe or a signal derived therefrom, and a core clock signal or a signal derived therefrom.

Abstract: In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.

Abstract: In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: generate a core clock; generate a capture clock; receive a data (DQ) signal that is driven by a DDR memory, or a signal derived from the DQ signal; clock a first core domain register, based, at least in part, on the capture clock; clock a second core domain register, based, at least in part, on the core clock; and set a delay of a core clock delay element, utilizing at least one of: the first core domain register, a signal derived from the first core domain register, the second core domain register, or a signal derived from the second core domain register; wherein the double data rate (DDR) memory controller is configured such that the delay of the core clock delay element is set during a power-on initialization calibration operation.

Abstract: A method for calibrating capturing read data in a read data path for a DDR memory interface circuit is described. In one version, the method includes the steps of delaying a core clock signal by a capture clock delay value to produce a capture clock signal and determining the capture clock delay value. The capture clock signal is a delayed version of the core clock signal. The timing for the read data path with respect to data propagation is responsive to at least the capture clock signal. In another version, timing for data capture is responsive to a read data strobe or a signal derived therefrom, and a core clock signal or a signal derived therefrom.

Abstract: A method for calibrating capturing read data in a read data path for a DDR memory interface circuit is described. In one version, the method includes the steps of delaying a core clock signal by a capture clock delay value to produce a capture clock signal and determining the capture clock delay value. The capture clock signal is a delayed version of the core clock signal. The timing for the read data path with respect to data propagation is responsive to at least the capture clock signal. In another version, timing for data capture is responsive to a read data strobe or a signal derived therefrom, and a core clock signal or a signal derived therefrom.

Abstract: A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation.

Abstract: A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method and a first set of values is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, establishing a second set of values. Several fringe timing points are sampled. A drift amount is compared with a drift correction threshold value and the first optimal sampling point is shifted in time by the drift amount to revise the first optimal sampling point.

Abstract: A method for calibrating capturing read data in a read data path for a DDR memory interface circuit is described. In one version, the method includes the steps of delaying a core clock signal by a capture clock delay value to produce a capture clock signal and determining the capture clock delay value. The capture clock signal is a delayed version of the core clock signal. The timing for the read data path with respect to data propagation is responsive to at least the capture clock signal. In another version, timing for data capture is responsive to a read data strobe or a signal derived therefrom, and a core clock signal or a signal derived therefrom.

Abstract: Circuits and methods are described for a DDR memory controller where two different DQS gating modes are utilized. These gating modes together ensure that the DQS signal, driven by a DDR memory to the memory controller, is only available when read data is valid. Two types of gating logic are used: Initial DQS gating logic, and Functional DQS gating logic. The Initial gating logic has additional timing margin in the Initial DQS gating value to allow for the unknown round trip timing during initial bit levelling calibration. DQS functional gating is then optimized during further calibration to gate DQS precisely as latency and phase calibration are performed, resulting in a precise gating value for Functional DQS gating. Providing dual gating modes is especially useful when data capture is performed at half the DQS frequency in view of rising clock rates for DDR memories.

Abstract: A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation.

Abstract: Circuits and methods are described for a DDR memory controller where two different DQS gating modes are utilized. These gating modes together ensure that the DQS signal, driven by a DDR memory to the memory controller, is only available when read data is valid. Two types of gating logic are used: Initial DQS gating logic, and Functional DQS gating logic. The Initial gating logic has additional timing margin in the Initial DQS gating value to allow for the unknown round trip timing during initial bit levelling calibration. DQS functional gating is then optimized during further calibration to gate DQS precisely as latency and phase calibration are performed, resulting in a precise gating value for Functional DQS gating. Providing dual gating modes is especially useful when data capture is performed at half the DQS frequency in view of rising clock rates for DDR memories.

Abstract: Circuits and methods are described for a DDR memory controller where two different DQS gating modes are utilized. These gating modes together ensure that the DQS signal, driven by a DDR memory to the memory controller, is only available when read data is valid. Two types of gating logic are used: Initial DQS gating logic, and Functional DQS gating logic. The Initial gating logic has additional timing margin in the Initial DQS gating value to allow for the unknown round trip timing during initial bit levelling calibration. DQS functional gating is then optimized during further calibration to gate DQS precisely as latency and phase calibration are performed, resulting in a precise gating value for Functional DQS gating. Providing dual gating modes is especially useful when data capture is performed at half the DQS frequency in view of rising clock rates for DDR memories.

Abstract: A continuously adaptive timing calibration function for a data interface is disclosed. A first calibration method is performed for a mission data path, typically at power-on, to establish an optimal sample point. Reference data paths are established for a second calibration method that does not disturb normal system operation. Data bit edge transitions are examined at fringe timing points on either side of the optimal sample point. Assuming that a timing change for the edge transitions indicates a drift of the optimal sample point, when a drift amount is determined to be greater than a correction threshold value the optimal sampling point for the mission path is adjusted accordingly. At no point does the continuous calibration function determine that any data bit is invalid since the optimal sampling point is always maintained. Also, at no point does continuous calibration require successive alternating data bit values such as 1-0-1 or 0-1-0.

Abstract: Techniques are described for providing additional content that is relevant to an upcoming service appointment in an audible format. The additional content can be retrieved from remote sources and aggregated to form an audio package to be played back to the technician as the technician travels to a destination address that corresponds with the upcoming service appointment. The additional content retrieved can depend on the estimated travel time to the destination address. By presenting the additional content audibly at the same time as route directions are being presented graphically, the driver can multi-task which results in time savings since the additional content has been consumed during the drive to the upcoming appointment rather than when the technician arrives at the destination address.

Abstract: Circuits and methods are described for a DDR memory controller where two different DQS gating modes are utilized. These gating modes together ensure that the DQS signal, driven by a DDR memory to the memory controller, is only available when read data is valid. Two types of gating logic are used: Initial DQS gating logic, and Functional DQS gating logic. The Initial gating logic has additional timing margin in the Initial DQS gating value to allow for the unknown round trip timing during initial bit levelling calibration. DQS functional gating is then optimized during further calibration to gate DQS precisely as latency and phase calibration are performed, resulting in a precise gating value for Functional DQS gating. Providing dual gating modes is especially useful when data capture is performed at half the DQS frequency in view of rising clock rates for DDR memories.

Abstract: A continuously adaptive timing calibration function for a data interface is disclosed. A first calibration method is performed for a mission data path, typically at power-on, to establish an optimal sample point. Reference data paths are established for a second calibration method that does not disturb normal system operation. Data bit edge transitions are examined at fringe timing points on either side of the optimal sample point. Assuming that a timing change for the edge transitions indicates a drift of the optimal sample point, when a drift amount is determined to be greater than a correction threshold value the optimal sampling point for the mission path is adjusted accordingly. At no point does the continuous calibration function determine that any data bit is invalid since the optimal sampling point is always maintained. Also, at no point does continuous calibration require successive alternating data bit values such as 1-0-1 or 0-1-0.

Abstract: Techniques are described for providing additional content that is relevant to an upcoming service appointment in an audible format. The additional content can be retrieved from remote sources and aggregated to form an audio package to be played back to the technician as the technician travels to a destination address that corresponds with the upcoming service appointment. The additional content retrieved can depend on the estimated travel time to the destination address. By presenting the additional content audibly at the same time as route directions are being presented graphically, the driver can multi-task which results in time savings since the additional content has been consumed during the drive to the upcoming appointment rather than when the technician arrives at the destination address.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.