Patents by Inventor Venkat Kolagunta

Venkat Kolagunta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020151167
    Abstract: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.
    Type: Application
    Filed: June 20, 2002
    Publication date: October 17, 2002
    Inventors: Janos Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat Kolagunta, John Mendonca, Rajesh Tiwari, Suresh Venkatesan
  • Patent number: 6444569
    Abstract: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: September 3, 2002
    Assignee: Motorola, Inc.
    Inventors: Janos Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat Kolagunta, John Mendonca, Rajesh Tiwari, Suresh Venkatesan
  • Publication number: 20010027083
    Abstract: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.
    Type: Application
    Filed: April 16, 2001
    Publication date: October 4, 2001
    Inventors: Janos Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat Kolagunta, John Mendonca, Rajesh Tiwari, Suresh Venkatesan
  • Patent number: 6274478
    Abstract: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scrubber.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: August 14, 2001
    Assignee: Motorola, Inc.
    Inventors: Janos Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat Kolagunta, John Mendonca, Rajesh Tiwari, Suresh Venkatesan