Patents by Inventor Venkat Kolagunta

Venkat Kolagunta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8741743
    Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (219); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (229); and (c) using the first and second masks to create a semiconductor device.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Omar Zia, Nigel Cave, Venkat Kolagunta, Ruiqi Tian, Edward O. Travis
  • Patent number: 7565639
    Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and a first epitaxial growth mask set (309) from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset (305) of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set (308).
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: July 21, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Omar Zia, Nigel Cave, Venkat Kolagunta, Ruiqi Tian, Edward O. Travis
  • Patent number: 7470624
    Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: December 30, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Omar Zia, Nigel Cave, Venkat Kolagunta, Ruiqi Tian, Edward O. Travis
  • Publication number: 20080166859
    Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (219); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (229); and (c) using the first and second masks to create a semiconductor device.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 10, 2008
    Inventors: Omar Zia, Nigel Cave, Venkat Kolagunta, Ruiqi Tian, Edward O. Travis
  • Publication number: 20080168418
    Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.
    Type: Application
    Filed: January 8, 2007
    Publication date: July 10, 2008
    Inventors: Omar Zia, Nigel Cave, Venkat Kolagunta, Ruiqi Tian, Edward O. Travis
  • Publication number: 20080168417
    Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and a first epitaxial growth mask set (309) from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset (305) of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set (308).
    Type: Application
    Filed: January 4, 2007
    Publication date: July 10, 2008
    Inventors: Omar Zia, Nigel Cave, Venkat Kolagunta, Ruiqi Tian, Edward O. Travis
  • Patent number: 7323373
    Abstract: A semiconductor device is formed by patterning a semiconductor layer to create a vertical active region and a horizontal active region, wherein the horizontal active region is adjacent the vertical active region. The semiconductor layer overlies an insulating layer. A spacer is formed adjacent the vertical active region and over a portion of the horizontal active region. At least a portion of the horizontal active region is oxidized to form an isolation region. The spacer is removed. A gate dielectric is formed over the vertical active region after removing the spacer. A gate electrode is formed over the gate dielectric. However, forming the spacer is optional.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: January 29, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, David C. Sing, Venkat Kolagunta
  • Publication number: 20070249127
    Abstract: An electronic device can include a substrate, an insulating layer, and a semiconductor layer overlying the insulating layer, wherein the insulating layer lies between the substrate and the semiconductor layer. In one aspect, a process of forming the electronic device can include patterning the semiconductor layer to define an opening extending to the insulating layer. The semiconductor layer has a sidewall and a surface, the surface is spaced apart from the insulating layer, and the sidewall extends from the surface towards the insulating layer. The process can also include forming a sidewall spacer adjacent to the sidewall, wherein the sidewall spacer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the sidewall spacer.
    Type: Application
    Filed: April 24, 2006
    Publication date: October 25, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Rode Mora, Vance Adams, Venkat Kolagunta, Michael Turner, Toni Van Gompel
  • Publication number: 20070235813
    Abstract: A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second semiconductor layer over the first active region and the seed layer, respectively. The first and second semiconductor layers can be spaced-apart from each other. In one aspect, the process can include selectively forming the first and second semiconductor layers simultaneously at a substantially same point in time. In another aspect, an electronic device can include first and second transistor structures separated by a field isolation region and electrically connected by a conductive member. A semiconductor island, designed to be electrically floating, can lie between the conductive member and the base layer.
    Type: Application
    Filed: April 10, 2006
    Publication date: October 11, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Omar Zia, Da Zhang, Venkat Kolagunta, Narayanan Ramani, Bich-Yen Nguyen
  • Publication number: 20070210381
    Abstract: An electronic device can have an insulating layer lying between a first semiconductor layer and a base layer. A second semiconductor layer, having a different composition and stress as compared to the first semiconductor layer, can overlie at least a portion of the first semiconductor layer. In one embodiment, a first electronic component can include a first active region that includes a first portion of the first and the second semiconductor layers. A second electronic component can include a second active region that can include a second portion of the first semiconductor layer. Different processes can be used to form the electronic device. In another embodiment, annealing a workpiece can be performed and the stress of at least one of the semiconductor layers can be changed. In a different embodiment, annealing the workpiece can be performed either before or after the formation of the second semiconductor layer.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 13, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Mariam Sadaka, Venkat Kolagunta, William Taylor, Victor Vartanian
  • Publication number: 20070172996
    Abstract: A semiconductor device is formed by patterning a semiconductor layer to create a vertical active region and a horizontal active region, wherein the horizontal active region is adjacent the vertical active region. The semiconductor layer overlies an insulating layer. A spacer is formed adjacent the vertical active region and over a portion of the horizontal active region. At least a portion of the horizontal active region is oxidized to form an isolation region. The spacer is removed. A gate dielectric is formed over the vertical active region after removing the spacer. A gate electrode is formed over the gate dielectric. However, forming the spacer is optional.
    Type: Application
    Filed: January 25, 2006
    Publication date: July 26, 2007
    Inventors: Leo Mathew, David Sing, Venkat Kolagunta
  • Publication number: 20070102755
    Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
    Type: Application
    Filed: November 8, 2005
    Publication date: May 10, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Vance Adams, Paul Grudowski, Venkat Kolagunta, Brian Winstead
  • Publication number: 20070090455
    Abstract: An electronic device can include a first transistor structure including a first gate electrode surrounded by a first sidewall spacer having a first stress and a second transistor structure including a second gate electrode surrounding a second sidewall spacer having second stress. The first sidewall spacer is an only sidewall spacer surrounding the first gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the first gate electrode and the second sidewall spacer is an only sidewall spacer surrounding the second gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the second gate electrode, wherein the first stress has a lower value as compared to the second stress. More than one process can be used to form the electronic device.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 26, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Sangwoo Lim, Stanley Filipiak, Paul Grudowski, Venkat Kolagunta
  • Publication number: 20060223335
    Abstract: A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area under the gate electrode and adjacent the first side of the gate electrode, a second area under the gate electrode and adjacent the second side of the gate electrode, and a third area under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.
    Type: Application
    Filed: March 29, 2005
    Publication date: October 5, 2006
    Inventors: Leo Mathew, Venkat Kolagunta, David Sing
  • Publication number: 20060065927
    Abstract: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Inventors: Voon-Yew Thean, Mariam Sadaka, Ted White, Alexander Barr, Venkat Kolagunta, Bich-Yen Nguyen, Victor Vartanian, Da Zhang
  • Publication number: 20060068553
    Abstract: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Inventors: Voon-Yew Thean, Mariam Sadaka, Ted White, Alexander Barr, Venkat Kolagunta, Bich-Yen Nguyen, Victor Vartanian, Da Zhang
  • Publication number: 20060043422
    Abstract: A transistor comprises a source and drain positioned within an active region. A gate overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive reduction feature extending from the source to the drain and underlying the gate for reducing capacitance associated with the gate, source and drain. The at least one stress modifier and capacitive reduction feature comprises dielectric and includes a shape defined at least partially by the active region.
    Type: Application
    Filed: August 24, 2004
    Publication date: March 2, 2006
    Inventors: Jian Chen, Michael Mendicino, Vance Adams, Choh-Fei Yeap, Venkat Kolagunta
  • Publication number: 20060043500
    Abstract: A transistor comprises an active region having a periphery with opposing sides and a source and a drain positioned within the active region. A gate overlies a channel area of the active region, the channel region separating the source and drain. The transistor further includes at least one stress modifying feature extending from an edge of the active region on at least one of a source side or a drain side and toward the channel area but not entering the channel area. The at least one stress modifying feature includes a dielectric.
    Type: Application
    Filed: August 24, 2004
    Publication date: March 2, 2006
    Inventors: Jian Chen, Michael Mendicino, Vance Adams, Choh-Fei Yeap, Venkat Kolagunta
  • Publication number: 20060024893
    Abstract: In one embodiment, a method for forming a semiconductor device is described. A semiconductor substrate has a first portion and a second portion. A first dielectric layer formed over the first portion of the semiconductor substrate and a second dielectric layer is formed over the second portion of the semiconductor substrate. A cap that may include silicon, such as polysilicon, is formed over the first dielectric layer. A first electrode layer is formed over the cap and a second electrode layer is formed over the second dielectric.
    Type: Application
    Filed: July 29, 2004
    Publication date: February 2, 2006
    Inventors: Byoung Min, Nigel Cave, Venkat Kolagunta, Omar Zia, Sinan Goktepeli
  • Patent number: 6573173
    Abstract: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: June 3, 2003
    Assignee: Motorola, Inc.
    Inventors: Janos Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat Kolagunta, John Mendonca, Rajesh Tiwari, Suresh Venkatesan