Abstract: A system and method for a memory device is disclosed. A substrate is provided. A first ferromagnetic layer is disposed over the substrate. A spacer layer is disposed over the first ferromagnetic layer. A second ferromagnetic layer is disposed over the spacer layer and magnetized in a first direction. A first charge current pulse is passed through the substrate, along a direction perpendicular to the first direction and orients the magnetization of the first ferromagnetic layer in a second direction perpendicular to the first direction. A second charge current pulse is passed through the substrate to selectively switch the magnetization of the first ferromagnetic layer either in the first direction or a direction opposite to the first direction based on a direction of the second charge current. The direction of switched orientation of the magnetization of the first ferromagnetic layer indicates a first value or a second value.

Abstract: A system and method for a device is disclosed. A first logic device and a second logic device are provided. Each of the first logic device and the second logic device include at least three inputs and one output, wherein, the output is based on majority of the inputs. The output of the first logic device is selectively fed to the second logic device, wherein, the first logic device and the second logic device together form an adder circuit.

Abstract: A computing system includes (1) a primary processor executing executable instructions and generating first instruction data associated with the executable instructions, (2) a secondary processor executing the executable instructions one or more clock cycles behind the primary processor and generating secondary instruction data associated with the executable instructions, (3) a first first-in first-out (FIFO) buffer for the primary processor, (4) a second FIFO buffer for the secondary processor, (5) circuitry storing at least some of the first instruction data in the first FIFO buffer and at least some of the second instruction data in the second FIFO buffer, (6) compare circuitry comparing a first portion of first instruction data and a second portion of second instruction data that are associated with a given clock cycle, and (7) control circuitry halting the primary and secondary processors responsive to a mismatch between the first portion and the second portion.

Abstract: A system and method for a logic device is disclosed. A substrate is provided. Three nanotracks are disposed over the substrate and intersect in a central portion. Two nanotracks are disposed about a first axis and one nanotrack is disposed about a second axis perpendicular to the first axis. A ground pad is disposed in the central portion. An input value is set by nucleating a skyrmion about a first end of the nanotracks disposed about the first axis. Presence of the skyrmion indicates a first value and absence indicates a second value. A charge current is passed in the substrate, along the first axis to move the nucleated skyrmions towards the central portion. Presence of the skyrmion is sensed in the central portion and indicates a first value when skyrmion is present.

Abstract: A system and method for a logic device is disclosed. Three synthetic antiferromagnet (SAF) nanotracks are disposed over a substrate along a first axis. A connector nanotrack connects the three input nanotrack about a second end of the nanotracks. An output nanotrack is disposed about a central portion of the connector nanotrack. An input value is defined at a first end of the input nanotracks by selectively nucleating a SAF skyrmion at the first end. Presence of the skyrmion is indicative of a first value and absence of the skyrmion indictive of a second value. A charge current is passed along the first axis to selectively move nucleated skyrmion to the output nanotrack, with presence of Skyrmion indicating an output value of the first value.

Abstract: A system and method for a logic device is disclosed. A plurality of synthetic antoferromagnet (SAF) nanotracks including a first input nanotrack, a second input nanotrack and an output nanotrack are disposed over a substrate along a first axis. Output nanotrack is disposed between the input nanotracks. Each nanotrack have a first end and a second end. A SAF connector nanotrack connects the first input nanotrack, the second input nanotrack, and the output nanotrack. An input value is defined at a first end of the input nanotracks by selectively nucleating a SAF skyrmion at the first end. Presence of the skyrmion is indicative of a first value and absence of the skyrmion indictive of a second value. A charge current is passed along the first axis to move nucleated skyrmion to the second end of the output nanotrack. Skyrmion at the output indicates an output value of the first value.

Abstract: A system and method for a logic device is disclosed. A plurality of substrates are provided. At least one input nanomagnet is disposed over each of the plurality of substrates. The plurality of input nanomagnets are disposed substantially equidistant from each other. The plurality of input nanomagnets are each a single domain nanomagnet. A spacer layer is disposed over the plurality of input nanomagnets. An output magnet is disposed over the spacer layer.

Abstract: A system and method for a logic device is disclosed. A first input nanotrack, a second input nanotrack and an output nanotrack are disposed over a substrate along a first axis. Output nanotrack is disposed between the input nanotracks. Each nanotrack have a first end and a second end. A connector nanotrack connects the first input nanotrack, the second input nanotrack, and the output nanotrack. An input value is defined at a first end of the input nanotracks by selectively nucleating a skyrmion at the first end. Presence of the skyrmion is indicative of a first value and absence of the skyrmion indictive of a second value. Nucleated skyrmion moves to the second end of the output nanotrack when a charge current is passed along the first axis. Presence of the skyrmion at the second end indicates an output value of the first value.

Abstract: A multi-thread communication system has several communications processors operative over a single interface for transmitting and receiving packets. The multi-thread communications processor is operative to sequentially handle multiple thread processes for each communications processor on a cycle by cycle basis according to a thread map register which determines the order of execution and how many cycles of a particular thread occur during a canonical interval.

Abstract: A system and method for a switching network is disclosed. A plurality of first switching assemblies, second switching assemblies and intermediate switching assemblies with each of the first switching assemblies, second switching assemblies and intermediate switching assemblies having at least two input ports and output ports is provided. Selective one of the two input ports is configured to receive a data to be processed and delivered at a designated one of the output ports. Received data passes through one or more selective first switching assemblies, one or more intermediate switching assemblies and one or more selective second switching assemblies, before the received data is delivered to the designated port. A plurality of additional data is received in one or more of the input ports to be delivered to one or more designated output ports is processed before the received data is delivered to the designated one of the output ports.

Abstract: A secure processor with fault detection has a core thread which executes with a redundant branch processor thread. In one configuration, the core thread is operative on a fully functional core processor configured to execute a complete instruction set, and the redundant branch processor thread contains only initialization instructions and flow control instructions such as branch instructions and is operative on a redundant branch processor which is configured to execute a subset of the complete instruction set, specifically a branch control variable initialization and a branch instruction, thereby greatly simplifying the redundant branch processor architecture. Fault conditions are detected by comparing either a history of branch taken/not taken and branch targets, or a comparison of program counter activity for the core thread and redundant branch processor thread.

Abstract: A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.

Abstract: A multi-thread communication system has several communications processors operative over a single interface for transmitting and receiving packets. The multi-thread communications processor is operative to sequentially handle multiple thread processes for each communications processor on a cycle by cycle basis according to a thread map register which determines the order of execution and how many cycles of a particular thread occur during a canonical interval.

Abstract: A system and method for a logic device is disclosed. A substrate is provided. Three nanotracks are disposed over the substrate and intersect in a central portion. Two nanotracks are disposed about a first axis and one nanotrack is disposed about a second axis perpendicular to the first axis. A ground pad is disposed in the central portion. Nanotrack along the second axis extend beyond the central portion to define an output portion. An input value is set by nucleating a skyrmion about a first end of the nanotracks. Presence of the skyrmion indicates a first value and absence indicates a second value. A charge current is passed in the substrate, along the first axis and the second axis to move the nucleated skyrmions towards the central portion. Presence of the skyrmion is sensed in the output portion and indicates a first value when skyrmion is present.

Abstract: A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.

Abstract: A communication processor is operative to adapt the thread allocation to communications processes handled by a multi-thread processor on an instruction by instruction basis. A thread map register controls the allocation of each processor cycle to a particular thread, and the thread map register is reprogrammed as the network process loads for a plurality of communications processors such as WLAN, Bluetooth, Zigbee, or LTE have load requirements which increase or decrease. A thread management process may dynamically allocate processor cycles to each respective process during times of activity for each associated communications process.

Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Abstract: A data storage system has a CPU data bus for reading and writing data to data accelerators. Each data accelerator has a controller which receives the read and write requests and determines whether to read or write a local cache memory in preprocessed form or an attached accelerator memory which has greater size capacity based on entries in an address translation table (ATT) and saves data in a raw unprocessed form. The controller may also include an address translation table for mapping input addresses to memory addresses and indicating the presence of data in preprocessed form.

Abstract: A multi-stage processor has a pre-fetch stage, and a sequence of pipelined processor stages. A thread map register contains thread identifiers, and a thread map valid register has locations corresponding to the thread map register and indicating whether a value in the thread map register is to be fetched or not, and a thread map length register indicates the number of thread map register locations forming a canonical sequence of thread identifiers to the pre-fetch stage. The pre-fetch stage does not act on a thread identifier with a not valid thread map valid value, thereby saving power in low demand conditions.

Abstract: A system and method for a memory device is disclosed. A substrate is provided. A nucleation pad is disposed over the substrate. A nanowire is disposed substantially perpendicular, about a center of the nucleation pad. A charge current is selectively passed through the substrate to nucleate a magnetic vortex in the nucleation pad, the magnetic vortex indicative of a magnetic domain and a direction of the magnetic vortex indicative of a polarity of the magnetic domain. A shift current is applied through the nanowire to shift the magnetic domain into the nanowire.