Abstract: A system and method for a memory device is disclosed. A substrate is provided. A nucleation pad is disposed over the substrate. A nanowire is disposed substantially perpendicular, about a center of the nucleation pad. A charge current is selectively passed through the substrate to nucleate a magnetic vortex in the nucleation pad, the magnetic vortex indicative of a magnetic domain and a direction of the magnetic vortex indicative of a polarity of the magnetic domain. A shift current is applied through the nanowire to shift the magnetic domain into the nanowire.

Abstract: A system and method for a logic device is disclosed. A first substrate, and a second substrate is provided, which are spaced apart from each other and manifests Spin orbit torque effect. A nanomagnet is disposed over the first substrate and the second substrate. A first charge current is passed through the first substrate and a second charge current is passed through the second substrate. A direction of flow of the first charge current and the second charge current defines an input value of either a first value or a second value. A spin in the nanomagnet is selectively oriented based on the direction of flow of the first charge current and the second charge current. The spin in the nanomagnet is selectively read to determine an output value as the first value or the second value. The logic device is configured as a XOR logic.

Abstract: A system and method for a logic device is disclosed. A first nanotrack along a first axis and a second nanotrack along a second axis perpendicular to the first axis are disposed over a substrate. The second nanotrack is disposed over the first nanotrack in a overlap portion. An input value is defined about a first end of the first nanotrack and the second nanotrack by nucleating a skyrmion, wherein a presence of the skyrmion defines a first value and absence of the skyrmion defines a second value. The nucleated skyrmion moves towards the second end of the nanotracks when a charge current is passed through the first nanotrack and the second nanotrack along the second axis. The presence of the skyrmion sensed at the second end of the nanotrack indicates an output value of the first value.

Abstract: A fault detecting multi-thread pipeline processor with fault detection is operative with a single pipeline stage which generates branch status comprising at least one of branch taken/not_taken, branch direction, and branch target. A first thread has control and data instructions, the control instructions comprising loop instructions including unconditional and conditional branch instructions, loop initialization instructions, loop arithmetic instructions, and no operation (NOP) instructions. A second thread has only control instructions and either has the non-control instructions replaced with NOP instructions, or removed entirely. A fault detector compares the branch status of the first thread and second thread and asserts a fault output when they do not match.

Abstract: A multiplier device for binary magnetic applied fields uses Interlayer Exchange Coupling (IEC) structure where two layers of ferromagnetic material are separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. A plurality of regions on a top surface are activated with a magnetic field in a first direction for a 1 value and in an opposite direction for a 0 value, the multiplication result presented as magnetic field direction on a plurality of output ferromagnetic regions.

Abstract: A system and method for a logic device is disclosed. A plurality of nanotracks are disposed over a substrate, along a first axis, with at least a left nanotrack, a right nanotrack and a middle nanotrack disposed between the left nanotrack and the right nanotrack. At least one connector nanotrack is disposed to connect two adjacent nanotracks. An input value is defined at a first end of the plurality of nanotracks by selectively nucleating a skyrmion at the first end. Presence of the skyrmion is indicative of a first value and absence of the skyrmion indictive of a second value. The nucleated skyrmion moves towards the second end of the nanotrack when a charge current is passed along the first axis. The presence of the skyrmion sensed at the second end of the middle nanotrack indicates an output value of the first value.

Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.

Abstract: A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.

Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Abstract: A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.

Abstract: A process for iterating through a multi-dimensional array has an iteration process and an address generation process. In one example of the invention an input address process, a coefficient address process, and an output address process generate addresses for a convolutional neural network (CNN. Each of the input address process, coefficient address process, and output address process is coupled to a plurality of iteration variables generated by an iteration variable process, each iteration variable process having an associated with a bound and stride for each iteration variable, thereby generating an input address, a coefficient address, and an output address.

Abstract: A system and method for a logic device is disclosed. A first substrate, a second substrate and a third substrate is provided. A first input nanomagnet is disposed over the first substrate, a second input nanomagnet is disposed over the second substrate, and a third input nanomagnet is disposed over the third substrate. A spacer layer is disposed over the first input nanomagnet, the second input nanomagnet, and the third input nanomagnet. An output magnet is disposed over the spacer layer.

Abstract: A node mesh contains an originating node and several node groups, each node group consisting of one or more nodes with interfaces connected to other nodes of the node group. Each node of a node group has an associated route table with an association between an applied DC voltage and an output interface to couple the input signal to. When the originating node outputs a DC voltage accompanied by differential signaling, each node in turn directs the DC voltage and differential signaling to an output interface as directed by the node local route table to a local termination in a node, which may be coupled to a training processor of inference processor for machine learning applications.

Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Abstract: The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).

Abstract: An adder device for binary magnetic applied fields uses Interlayer Exchange Coupling (IEC) structure where two layers of ferromagnetic material are separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. A set of regions are positioned on a top layer above a continuous bottom layer, and the regions excited with magnetization for A and not A, B and not B, and C and not C to form a sum and an inverse carry output magnetization.

Abstract: A node mesh contains an originating node coupled to one or more nodes, each node having an communications interface input and a communications interface output. Each node has a route table with an association between a header amplitude and an output interface, such that a header having a particular amplitude causes the input node which received the message to couple the message to an associated communications interface output of the node. When the originating node outputs a message with a header amplitude, each node of the node mesh in turn directs the message to an output interface as directed by the node local route table to a terminating node of the node mesh, where the terminating node may be a training processor or inference processor for machine learning applications.

Abstract: A secure processor with fault detection has a core thread which executes with a redundant branch processor thread. In one configuration, the core thread is operative on a fully functional core processor configured to execute a complete instruction set, and the redundant branch processor thread contains only initialization instructions and flow control instructions such as branch instructions and is operative on a redundant branch processor which is configured to execute a subset of the complete instruction set, specifically a branch control variable initialization and a branch instruction, thereby greatly simplifying the redundant branch processor architecture. Fault conditions are detected by comparing either a history of branch taken/not taken and branch targets, or a comparison of program counter activity for the core thread and redundant branch processor thread.

Abstract: A fault detecting multi-thread pipeline processor with fault detection is operative with a single pipeline stage which generates branch status comprising at least one of branch taken/not_taken, branch direction, and branch target. A first thread has control and data instructions, the control instructions comprising loop instructions including unconditional and conditional branch instructions, loop initialization instructions, loop arithmetic instructions, and no operation (NOP) instructions. A second thread has only control instructions and either has the non-control instructions replaced with NOP instructions, or removed entirely. A fault detector compares the branch status of the first thread and second thread and asserts a fault output when they do not match.

Abstract: A task processor has a low power connectivity processor and a high performance applications processor. Software processes have a component operative on a connectivity processor and a component operative on an applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.