Patents by Inventor Venkat R. Indukuru

Venkat R. Indukuru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10895947
    Abstract: Mechanisms are provided for a graphical user interface tool for system-wide topology and performance monitoring with per-partition views. A graphical user interface application presents a consolidated view of physical and logical information based on the received performance data. The mechanisms provide real-time performance and utilization information in a visual format relative to the physical components in a topographical layout. The user may drill down to lower levels to view more detailed performance and utilization information.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: January 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: William A Bostic, Randall R. Heisch, Venkat R. Indukuru, Allan E. Johnson, Jesse L. Sathre, Philip L. Vitale
  • Patent number: 10310830
    Abstract: Systems, methods, and computer readable media to improve the development of image processing intensive programs are described. In general, techniques are disclosed to non-intrusively monitor the run-time performance of shader programs on a graphics processing unit (GPU)—that is, to profile shader program execution. More particularly, the shader profiling comprises of sampling data during the execution of a compiled code on GPU. The execution duration of the sequences of instructions within the code is determined. Subsequently, based relative latency of the instructions within the sequence, the duration time for each binary instruction is determined. The binary instructions are then mapped to source code in order to obtain the amount of time each source code instruction in a shader take to execute per draw call.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 4, 2019
    Assignee: Apple Inc.
    Inventors: Syed Irfan Zaidi, Sun Tjen Fam, Puyan Lotfi, Venkat R. Indukuru, Jun Pan, Andrew M. Sowerby, Jean-Luc Duprat
  • Publication number: 20190114035
    Abstract: Mechanisms are provided for a graphical user interface tool for system-wide topology and performance monitoring with per-partition views. A graphical user interface application presents a consolidated view of physical and logical information based on the received performance data. The mechanisms provide real-time performance and utilization information in a visual format relative to the physical components in a topographical layout. The user may drill down to lower levels to view more detailed performance and utilization information.
    Type: Application
    Filed: December 3, 2018
    Publication date: April 18, 2019
    Inventors: William A. Bostic, Randall R. Heisch, Venkat R. Indukuru, Allan E. Johnson, Jesse L. Sathre, Philip L. Vitale
  • Patent number: 10241889
    Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heather L. Hanson, Venkat R. Indukuru, Francis P. O'Connell, Karthick Rajamani
  • Publication number: 20180349119
    Abstract: Systems, methods, and computer readable media to improve the development of image processing intensive programs are described. In general, techniques are disclosed to non-intrusively monitor the run-time performance of shader programs on a graphics processing unit (GPU)—that is, to profile shader program execution. More particularly, the shader profiling comprises of sampling data during the execution of a compiled code on GPU. The execution duration of the sequences of instructions within the code is determined. Subsequently, based relative latency of the instructions within the sequence, the duration time for each binary instruction is determined. The binary instructions are then mapped to source code in order to obtain the amount of time each source code instruction in a shader take to execute per draw call.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 6, 2018
    Inventors: Syed Irfan Zaidi, Sun Tjen Fam, Puyan Lotfi, Venkat R. Indukuru, Jun Pan, Andrew M. Sowerby, Jean-Luc Duprat
  • Patent number: 10146396
    Abstract: Mechanisms are provided for a graphical user interface tool for system-wide topology and performance monitoring with per-partition views. A graphical user interface application presents a consolidated view of physical and logical information based on the received performance data. The mechanisms provide real-time performance and utilization information in a visual format relative to the physical components in a topographical layout. The user may drill down to lower levels to view more detailed performance and utilization information.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: William A. Bostic, Randall R. Heisch, Venkat R. Indukuru, Allan E. Johnson, Jesse L. Sathre, Philip L. Vitale
  • Patent number: 9921953
    Abstract: A hint bit detection and correction method and system that uses two additional bits as part of every cache directory. These bits represent the lwarx and stwcx instructions (larx disp, stcx disp). When a hint bit event occurs, depending the on combination of these two bits, there can be an indication of a hint bit error. Once a hint bit error is detected a software interrupt is issued and the hint bit correction method identifies and corrects the incorrect hint bit.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin Carter Nowak, Guy Lynn Guthrie, Venkat R Indukuru
  • Publication number: 20170177275
    Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 22, 2017
    Inventors: HEATHER L. HANSON, VENKAT R. INDUKURU, FRANCIS P. O'CONNELL, KARTHICK RAJAMANI
  • Patent number: 9652356
    Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: May 16, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heather L. Hanson, Venkat R. Indukuru, Francis P. O'Connell, Karthick Rajamani
  • Patent number: 9600392
    Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heather L. Hanson, Venkat R. Indukuru, Francis P. O'Connell, Karthick Rajamani
  • Publication number: 20170068545
    Abstract: A hint bit detection and correction method and system that uses two additional bits as part of every cache directory. These bits represent the lwarx and stwcx instructions (larx disp, stcx disp). When a hint bit event occurs, depending the on combination of these two bits, there can be an indication of a hint bit error. Once a hint bit error is detected a software interrupt is issued and the hint bit correction method identifies and corrects the incorrect hint bit.
    Type: Application
    Filed: September 9, 2015
    Publication date: March 9, 2017
    Inventors: Benjamin Carter Nowak, Guy Lynn Guthrie, Venkat R. Indukuru
  • Publication number: 20160364332
    Abstract: A hint bit detection and correction method uses two additional bits as part of every cache directory. These bits represent the lwarx and stwcx instructions (larx disp, stcx disp). When a hint bit event occurs, depending the on combination of these two bits, there can be an indication of a hint bit error. Once a hint bit error is detected a software interrupt is issued and the hint bit correction method identifies and corrects the incorrect hint bit.
    Type: Application
    Filed: June 10, 2015
    Publication date: December 15, 2016
    Inventors: Benjamin Carter Nowak, Guy Lynn Guthrie, Venkat R. Indukuru
  • Patent number: 9514046
    Abstract: A hint bit detection and correction method uses two additional bits as part of every cache directory. These bits represent the lwarx and stwcx instructions (larx disp, stcx disp). When a hint bit event occurs, depending the on combination of these two bits, there can be an indication of a hint bit error. Once a hint bit error is detected a software interrupt is issued and the hint bit correction method identifies and corrects the incorrect hint bit.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Benjamin Carter Nowak, Guy Lynn Guthrie, Venkat R. Indukuru
  • Patent number: 9495170
    Abstract: During a pipeline stall in a processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from functional units of the processor, finish reports including completion reasons for separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the finish reports. Once the monitoring unit receives a complete indicator from the completion unit, indicating the completion of the next to complete instruction group, the monitoring unit stores each determined stall reason aligned with each next to finish indicator in memory.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Venkat R. Indukuru, Brian R. Konigsburg, Alexander E. Mericas, Benjamin W. Stolt
  • Patent number: 9405548
    Abstract: Methods, systems, and computer program products may provide delay-identification in data processing systems. An apparatus may include a delay-identification unit having a delay counter, a threshold register, a delay register, and a delay detector. The delay detector may be configured to start the delay counter in response to detecting that one group of instructions is delayed, and stop the delay counter in response to detecting that the one group of instructions is no longer delayed. The delay detector may additionally be configured to compare the number of cycles counted by the delay counter with a threshold number of cycles in the threshold register, and store at least one effective address of one of the instructions of the one group of instructions when the number of cycles counted by the delay counter is greater than the threshold number of cycles stored in the threshold register.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: August 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Venkat R Indukuru, Alexander E Mericas
  • Publication number: 20160202848
    Abstract: Mechanisms are provided for a graphical user interface tool for system-wide topology and performance monitoring with per-partition views. A graphical user interface application presents a consolidated view of physical and logical information based on the received performance data. The mechanisms provide real-time performance and utilization information in a visual format relative to the physical components in a topographical layout. The user may drill down to lower levels to view more detailed performance and utilization information.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: William A. Bostic, Randall R. Heisch, Venkat R. Indukuru, Allan E. Johnson, Jesse L. Sathre, Philip L. Vitale
  • Patent number: 9317427
    Abstract: According to one aspect of the present disclosure a method and technique for managing memory access is disclosed. The method includes setting a memory databus utilization threshold for each of a plurality of processors of a data processing system to maintain memory databus utilization of the data processing system at or below a system threshold. The method also includes monitoring memory databus utilization for the plurality of processors and, in response to determining that memory databus utilization for at least one of the processors is below its threshold, reallocating at least a portion of unused databus utilization from the at least one processor to at least one of the other processors.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: April 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Donald R. DeSota, Rajendra D. Panda, Venkat R. Indukuru, Joseph H. Robichaux, Robert H. Bell, Jr., Steven P. Hartman
  • Patent number: 9298651
    Abstract: In-memory accumulation of hardware counts in a computer system is carried out by continuously sending count values from full-speed hardware counter units to a memory controller. A sending unit periodically samples performance data from the hardware counter units, and transmits count values to a bus interface for an interconnection bus which communicates with the memory controller. The memory controller responsively updates an accumulated count value stored in system memory using the current count value, e.g., incrementing the accumulated count value. A count value can be sent with a pointer to a memory location and an instruction on how the location is to be updated. The instruction may be an atomic read-modify-write operation, and the memory controller can include a dedicated arithmetic logic unit to carry out that operation. A data harvester can then be used to harvest accumulated count values by reading them from a table in system memory.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Heyrman, Venkat R. Indukuru, Carl E. Love, Aaron C. Sawdey, Philip L. Vitale
  • Patent number: 9292403
    Abstract: Mechanisms are provided for a graphical user interface tool for system-wide topology and performance monitoring with per-partition views. A graphical user interface application presents a consolidated view of physical and logical information based on the received performance data. The mechanisms provide real-time performance and utilization information in a visual format relative to the physical components in a topographical layout. The user may drill down to lower levels to view more detailed performance and utilization information.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: William A. Bostic, Randall R. Heisch, Venkat R. Indukuru, Allen E. Johnson, Jesse L. Sathre, Philip L. Vitale
  • Publication number: 20160041775
    Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.
    Type: Application
    Filed: May 28, 2015
    Publication date: February 11, 2016
    Inventors: HEATHER L. HANSON, VENKAT R. INDUKURU, FRANCIS P. O'CONNELL, KARTHICK RAJAMANI